Abstract: A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles.

Abstract: Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred direction that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout.

Abstract: In one embodiment, a method comprises partitioning a circuit description into a plurality of simulateable partitions. The partitioning is independent of a hierarchy specified in the circuit definition. The method also comprises sorting the plurality of simulateable partitions into one or more groups, wherein each simulateable partition included in a given group is equivalent to each other partition in the given group. Further, the method comprises simulating a first simulateable partition in the given group responsive to one or more input stimuli to the first simulateable partition. For each other simulateable partition in the given group that has approximately the same input stimuli as the first simulateable partition, the method still further comprises using a result of simulating the first simulateable partition as a result of the other simulateable partition.

Abstract: An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at feast one design phase or manufacturing phase of an article of manufacture having sub-lightwave structures and then detecting design phase or manufacturing phase defects in response to the filtering of the lithography simulation.

Abstract: Method and apparatus for implementing a task-based interface in a logic verification system is described. In some examples, a task server and a context memory are implemented in a hardware accelerator for a task. The task server is configured for communication with the logic design. A task stub configured for execution by a computer for the task is generated. Calls to the task are received from a test bench in the computer at the task stub. Remote procedure call (RPC) channels are established in response to the calls. Values of input arguments for the calls are transferred to the context memory through the RPC channels. Execution of threads of the task in the task server is triggered using the values of the input arguments in the context memory as parametric input.

Abstract: Method, apparatus, and computer readable medium for simulating a logic design having power domains are described. In some examples, a switchable power domain of the power domains is identified, the switchable power domain having primary inputs and having a power state switchable between a power-on state and a power-off state. The logic design is traversed to analyze driver and load logic of each of the primary inputs to the switchable power domain to identify any pure pass-through nets each of which has no driver and no load logic in the switchable power domain.

Abstract: Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by the assertion for a single attempt to evaluate the assertion. The evaluation engine is implemented in first reconfigurable hardware. The logic design is simulated over a plurality of clock events. Attempts to evaluate the assertion by the evaluation engine are preformed sequentially based on input stimuli obtained from the logic design during simulation thereof. Each of the attempts results in one of the assertion passing, the assertion failing, or the assertion requiring further evaluation.

Abstract: An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to avoid or minimize cross-capacitance problems on the IC design. A cost may be assigned to different candidate metal fill shapes. The cost is associated with the expected effect upon timing requirements by the metal fill shape, with lower costs corresponding to lower expected impacts upon the timing requirements. To meet density requirements, lower cost metal fill shapes are inserted prior to higher cost metal fill shapes.

Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method performs circuit pruning for each of distinct vectors. The circuit pruning includes identifying an active circuit for each vector. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed. The circuit pruning and circuit simulations are repeated for remaining ones of the plurality of substantially distinct vectors. The results of the circuit simulations are then stored on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.

Abstract: Method and apparatus for controlling power in an emulation system is described. In one example, power is controlled in a processor-based emulation system coupled to a host computer. A logic design is processed to identify unused resources in the emulation system during an emulation cycle. Power of the unused resources is controlled during emulation of a design under verification corresponding to the logic design by the emulation system. The resources may be identified as being unused during one or more steps of the emulation cycle. The power of the unused resources may be controlled by at least one of: powering down one or more of the unused resources; disabling one or more of the unused resources; freezing inputs to one or more of the unused resources; or setting inputs to one or more of the unused resources to a constant state. In this manner, power consumption of the emulation system is reduced.

Abstract: A method, system, and computer program product are disclosed for automatic test generation for a compiler. In one approach, the method, system and computer program product represent a test case for the compiler in a structure with one or more elements of a programming language, associate at least one syntactic rule and semantic rule with the one or more elements in the structure, create a test with the structure compiling the test with the compiler, and display results of the test.

Abstract: A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot spots determination.

Abstract: An improved approach for locating and identifying IP for an electronic design is described. The present approach addresses the situation in which an IP catalog does not contain any IP which matches the exact requirements of an electronic design for which the IP is to be used or integrated.

Abstract: Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved in the topological routing phase where the constraints of routing are less prohibitive. Multiple topological transformations directed toward resolving the overloads are executed in the topological routing phase prior to a geometric arrangement being realized. The topological transformations may be applied concurrently by way of a multi-threaded embodiment of the invention.

Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.

Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.

Abstract: A system and method for determining the criticality of each timing pin in a circuit design are disclosed. The criticality of a timing pin is the probability that the timing pin is on the path with the worst slack in the circuit design. According to the methodology, the slack for each timing pin is calculated, wherein each slack is a function of a process random variable. Then, the criticality of each timing pin is determined as the probability of the timing pin having the minimum slack among the slacks in an independent critical set of timing pins. The criticality of each timing pin may then be normalized. By determining the criticalities of the timing pins in a circuit design, a circuit design system may be able to more easily identify portions of the circuit design that need modification for timing and other purposes.

Abstract: An approach is provided for selectively optimizing a circuit design to be physical implemented. The approach includes generating a circuit routing solution in accordance with a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a plurality of corresponding constraint instances. Each constraint instance variably indicates an effective constraining limit and degree of consumption for at least one of the parametric resources. At least one of the constraints is selectively adjusted by a predetermined over-constraining amount, and the circuit routing solution is preliminarily modified by applying at least one routing action selected responsive to the constraint adjustment. An automatic evaluation is then made of the potential impact upon constraint compliance.

Abstract: An automated approach is provided for evaluating stress upon analog components embedded in a digital electronic circuit design. The approach includes establishing a computer readable circuit definition of the digital electronic circuit design. The circuit definition is then partitioned into a plurality of circuit portions, which are re-defined to form a plurality of analog topologies. The analog topologies are adapted for automatic analog simulation one independent of the other, with all digital components substituted by at least one subcircuit including instantiation of a corresponding input output (IO) buffer model. Automatic analog simulation is carried out upon the analog topologies to generate simulated results data, which are automatically postprocessed to generate worst-case stress measurement data for one or more critical components identified in the analog topologies.

Abstract: A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing.