Abstract: A computerized method for detecting errors in program code including searching for lines of command codes in the program code, wherein a line of command code includes a set of command codes and a set of indices; separating the sets of command codes from the sets of indices, wherein the sets of indices are a matrix; parsing the sets of command codes to locate three or more consecutive lines of command codes, which have the same sets of command codes; for the three or more consecutive lines of command codes, generating sets of vertical indices from vertically aligned indices in the matrix; determining if each set of vertical indices does not match at least one known series in a set of known series; and reporting to a user computer each set of vertical indices that does not match the at least one known series.

Abstract: A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

Abstract: A method and a system to pre-scan a file, analyze data and create the Condensed Macro Library (CML) file. The method used is to find macros or cells of certain classes that are defined by rules. After a suitable macro or cell is identified, a parser scans the macro or cell pins and finds pins which have ports with the shapes defined on the specific layers defined by the rules and user data. Further processing is then performed based on a set of rules and the pin data to generate a CML file that contains relevant information regarding relevant pins.

Abstract: Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.

Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays. An approach is described for performing memory mapping in the context of selecting an electronic product having an array of uncommitted logic.

Abstract: A method for automatically decomposing a shape of an IC design layout into two or more shapes in order to resolve a double patterning loop violation involving the shape. The method decomposes the shape by introducing one or more splicing graphs on the shape. These splicing graphs serve as cuts to be made on the shape. By decomposing the shape into several shapes and assigning the shapes to alternating masks for the same layer, the method breaks the double patterning loop. That is, no pair of the shape and other shapes that form the loop will be assigned to the same color for a mask after the shape is decomposed. In some embodiments, the method introduces splicing points to more than one shape of the loop-forming shapes when necessary. Some embodiments minimize the number of splicing points introduced to the shape(s).

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing a layout of an electronic circuit using one or more constraint checking windows. The method identifies some constraints on multiple-patterning lithography and multiple constraint checking windows for the layout. The method determines one or more metrics for a constraint checking window or for a layout and assigns one or more shapes in the one or more constraint checking windows to their respective mask designs based on the one or more metrics. The method traverses through the one or more constraint checking windows until all shapes in the layout are assigned to their respective mask designs. The method may also determine a processing order for the one or more constraint checking windows based on the distribution of a type of shapes in the layout.

Abstract: A method and system for auto-routing wiring within a PCB. In some embodiment, a first broad region within a first layer and a counterpart first broad region within a second layer are defined. The counterpart regions define a first broad via location. In some embodiments, the first and second broad via locations of the first and second layers can then be subdivided into a plurality of triangular regions. The triangular regions on the first and second layers can then be compared to more accurately locate an appropriate via location.

Abstract: A method, system, and computer program product are disclosed for using pattern-dependent models at early stages of the design process. This addresses the key disadvantage of prior approaches which are restricted to using such models later in the design process for IC designs that are nearly complete. Pattern-dependent manufacturing effects are extracted from early stage designs and using the extracted pattern-dependent effects to efficiently and effectively design the integrated circuit. One or more contexts are built around one or more units of the design, with examples of units being a block or cell. The units are then used in the context to generate pattern-dependent data as a basis for one or more pattern-dependent models.

Abstract: Disclosed are methods, systems, and articles of manufacture for processing a electronic design, which use a computer system to identify an operation associated with a task to be performed on the electronic design, to generate a hierarchical output for multiple shapes for performing the task based at least in part on performing an operation associated with the task, and to display or to store the hierarchical output. The task comprises a dummy fill insertion task or a design verification task in some embodiments. The methods or the systems may further determine or identify an inverse transform and apply the inverse transform to a shape before adding the shape to the hierarchical output. In some embodiments, there exists no duplication among the shapes in the hierarchical output, or only shapes derived from original shapes that belong to the first instance of a cellview master are added to the hierarchical output.

Abstract: In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.

Abstract: The present invention allows a verification environment to be used to control and coordinate interaction with a design running on an accelerator or emulator without significant speed penalty. For example, an interface capable of communicating with test software running on an embedded processor is used to control and monitor the flow of data into the external interface of the design. Thus, a connection is made between the verification environment and the design under test running on the accelerator/emulator via a connection formed directly between the verification environment and embedded software running on the emulator for simulation and monitoring purpose at a very low frequency so that high-speed acceleration may still be achieved.

Abstract: Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic designs. An improved approach for providing seamless interaction between analog and digital blocks during simulation, even if the digital blocks include complex types or models.

Abstract: In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Abstract: An improved approach is described for allowing designers to identify and utilize suitable IP for an electronic design. An architecture is provided that includes an IP portal and/or chip estimator to identify suitable IP from a catalog of IP, which is integrated with a hosted design environment to use and test that IP for the user's specific electronic design. An authorization mechanism may be used to control access to the IP from the IP catalog. This approach greatly enhances the probability that IP suppliers will be successfully connected with the target consumers of those IP blocks.

Abstract: A model library contains one or more storable models of a physical system each constructed by numerically solving relationships between a characteristic of the physical system given a set of model parameters. Such a model may be retrieved from the library according to values assigned to the model parameters and used to determine a corresponding characteristic of the physical system without repeating the numerical solution method originally used to create the model. Instead, a mapping may be applied to the storable model to seamlessly obtain the characteristic upon request.

Abstract: Techniques are presented for improving parametric yield. As part of an automatic sizing process for a circuit, one set of techniques receives a target value for a performance goal and then optimizes, with respect to the number of standard deviations, the distance by which the mean value of a distribution of the performance goal differs from the target value. In a second set of techniques, as part of an automatic sizing process during a circuit design process, the operation of the circuit is simulated to determine the distribution of a performance goal for a first design point. It is then determined whether a second design point is sufficiently close to the first design point and, if so, the simulation for the first design point is used for evaluating the second design point in an optimization process.