Abstract: Methods and systems for allowing an Integrated Circuit designer to specify one or more design rules, and to determine the expected probability of success of the IC design based on the design rules. Probability information is compiled for each circuit component, that specifies the probability of the circuit component working if a characteristic of the circuit component is varied. As the design rules are examined, the probability of each component working is calculated. The probabilities are combined to determine the overall probability of success for the IC design. Furthermore, the IC design may be broken into a plurality of portions, and design rules can be separately specified for each portion. This allows a designer the flexibility to use different design rules on different portions of the IC design.

Abstract: According to various embodiments of the invention, systems and methods are provided for compressed design phase contour data created during the manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a contour layout from a target layout during the design phase of a circuit. This contour layout is generated by way of a contour generator tool. Next, a set of differences between the contour layout and the target layout are calculated. A dataset containing these differences is generated. In some embodiments, the contour generator uses a post-optical proximity correction (OPC) layout of the target layout in order to generate the contour layout.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.

Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.

Abstract: An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.

Abstract: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform in parallel and sends the task to be performed in parallel; and receives execution results or processing results from some of the plurality of slaves and updates one or more databases to incorporate the execution or processing results. In some embodiments, the method allows speeding up the applications without major rewrite without a need for design partition, and without memory penalty.

Abstract: Achieving clock timing closure in designing an integrated circuit involves virtually synthesizing a clock network for the integrated circuit design to generate virtual clock buffering in the clock network before a point in the design flow at which the clock network is actually synthesized and committed to a netlist. Timing violations are determined for clock gates generated by the virtual clock buffering. Clock gating transforms are evaluated for the clock gates having the timing violations, based on recalculated clock and data path delays, to incrementally virtually synthesize the clock network. The clock gating transforms that result in the best timing gains are committed to the netlist. The clock network is then actually synthesized for the integrated circuit design, and design changes, due to the actual clock network synthesis, are committed to the netlist.

Abstract: A contract management mechanism is disclosed for managing contracts in the software licensing arena. The management mechanism may be used, for example, to manage one or more fulfillment contracts. In operation (assuming a software licensing implementation for the sake of example), the management mechanism receives an inquiry regarding licensing of a particular set of software under a particular contract (the contract entitles a customer to consume a certain quota of resources under the contract). In response to the inquiry, the management mechanism determines a licensing amount. This licensing amount may be determined based upon many factors, including the set of software selected, other parameters specified in the inquiry, and the terms associated with the contract. Once the licensing amount is determined, and the customer commits to licensing the software, the management mechanism reduces the quota parameter of the contract by the licensing amount and allows the software to be used under the contract.

Abstract: Disclosed are improved approaches for implementing design entry. An efficient, spread-sheet based representation is provided for both the instances and connections in a design. Visualization techniques provide the user with visual cues, to direct and identify compatible connection points, unconnected instances, and contention situations. Techniques are disclosed to automatically filter the spreadsheet in a variety of ways, to help the user to dynamically hide portions of the design space that are not interesting at a particular time, and thus to improve the efficiency with which they can work.

Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D MDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.

Abstract: A hardware emulator having a first primitive for evaluating functions having a first input width and a second primitive, coupled to the first primitive, for evaluating a function having a second input width, where the first input width is unequal to the second input width. The use of either the first primitive or the second primitive is selected depending upon the function to be evaluated.

Abstract: Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved in the topological routing phase where the constraints of routing are less prohibitive. Multiple topological transformations directed toward resolving the overloads are executed in the topological routing phase prior to a geometric arrangement being realized. The topological transformations may be applied concurrently by way of a multi-threaded embodiment of the invention.

Abstract: According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing the original layout of an integrated circuit pattern. The pattern matcher processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet a design waiver. The pattern matcher generates a second layout pattern with the waived patterns marked. The design rule checker subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules.

Abstract: A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of state correlation.

Abstract: A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.

Abstract: A CMOS phase interpolation system comprises a capacitive integration unit coupled to a charge node and a plurality of selectively enabled current source units operably coupled to the charge node. The current source units each include: a charging segment; a discharging segment; and, a switching segment operable responsive to at least one periodic reference signal to selectively couple the charging and discharging segments to the charge node for alternatively charging and discharging the capacitive integration unit therethrough. The current source units are selectively enabled in predetermined combinations to uniquely define an output waveform at the charge node. An output conditioning unit coupled to the charge node generates a recovered periodic signal based on the output waveform. In certain applications, a duty cycle correction unit coupled to feed back from the output node adaptively biases a charging segment current of each enabled current source unit, responsive to the recovered periodic signal.

Abstract: Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved in the topological routing phase where the constraints of routing are less prohibitive. Multiple topological transformations directed toward resolving the overloads are executed in the topological routing phase prior to a geometric arrangement being realized. The topological transformations may be applied concurrently by way of a multi-threaded embodiment of the invention.

Abstract: Various embodiments of the present invention are generally directed to a method, system, and computer program product for implementing direct measurement model with simulation and calibration of manufacturing process model in the manufacturing of precision devices such as electronic integrated circuits. The method and the system determine the measured measurement result and the direct measurement information and compare the direct measurement information against the other to determine whether to adjust the process models and the empirical parameters thereof.