Abstract: In one embodiment of the invention, an apparatus for scan testing an integrated circuit is provided. The apparatus includes a combinational logic network; and a device for reducing gate switching in the combinational logic network to reduce power consumption during a scan test on the combinational logic network. The device for reducing gate switching in the combinational logic network includes a device for periodically isolating scan data from the combination logic network; and a device for periodically holding functional data coupled into the combinational network substantially steady. In one embodiment of the invention, the device for reducing gate switching in the combinational logic network is a plurality of serially coupled scan registers each having a pair of opposed controlled outputs with one controlled output providing scan output data and another controlled output providing functional data to the combinational logic network.

Abstract: Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.

Abstract: Double patterning using a single reticle. A blading technique may be used to allow a single reticle to be used for double patterning. The reticle is placed into a lithographic apparatus and a first portion of the pattern is exposed onto a first photoresist overlaying a target region, while blading the second portion of the pattern. Then, a second portion of the pattern is exposed onto a second photoresist, while blading the first portion. Alternatively, each portion of the pattern may be exposed to the photoresist simultaneously, but to different target regions. Then shot coordinates are adjusted and the portions are exposed to a photoresist again to allow creation of the composite pattern in at least one of the target regions. During the double patterning process, the reticle may be kept in the lithographic apparatus.

Abstract: A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.

Abstract: In one embodiment, a method comprises partitioning a circuit description into simulateable partitions; sorting the simulateable partitions into classes wherein each simulateable partition included in a given class is equivalent to each other partition in the given class with a specified tolerance; associating a dynamic state machine with each class, wherein states of the dynamic state machine correspond to states reached by at least one simulateable partition in the given class during a simulation; during a simulation of the circuit description, the result of which is stored for user display: responsive to a current state in the dynamic state machine for a first simulateable partition in the given class and further responsive to input stimuli to the first simulateable partition, matching the one or more input stimuli to stimuli associated with a next state edge from the current state; and changing the current state of the first simulateable partition to a second state of the dynamic state machine indicated by

Abstract: A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of bi-exponential modeling.

Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.

Abstract: Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition.

Abstract: Various embodiments of the invention comprise methods and systems for determining when or whether to use hard rules or preferred rules during global routing of an electronic design. In some embodiments, the entire routable space is first routed with hard rules during global routing while ensuring the design may be embedded. The design is then analyzed with preferred rules where the overcongested areas are marked as “use hard rule” and areas not overcongested are marked as “use preferred rule.” The methods or the systems thus ensure that the design remains routable throughout the process while improving timing, manufacturability, or yield by reserving routing space for the preferred rules.

Abstract: A method is provided that performs a path search that identifies several path extensions. The method performs a viability check on a particular path extension by identifying first and second circuit geometries. The first circuit geometry is associated with a particular segment of a route that would result from the particular path expansion in a design layout. The second circuit geometry is associated with a circuit element to which the particular segment connects. The viability check also determines whether connecting the segment with the first geometry and the circuit element with the second geometry is allowable based on predetermined rules. The method stores the particular path expansion in a storage medium as a viable path expansion when the viability check determines that connecting the segment with the first geometry and the circuit element with the second geometry is allowable.

Abstract: In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.

Abstract: In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.

Abstract: A method and systems are provided for screening and rapid evaluation of routed nets in a post-layout circuit environment, such as in the design of printed circuit boards. A portion of nets are selected for determination of associated signal quality factors. Signal channels containing one or more selected nets are then built. A reference input stimulus is propagated along each of the signal channels in a frequency based simulation for generating characteristic responses of the selected nets' signal channels. A signal channel quality factor is obtained for each signal channel based upon its characteristic response. The signal channels and their nets are then comparatively analyzed according to corresponding signal channel quality factors to selectively identify any aberrant nets warranting supplemental evaluation for faults.

Abstract: A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design.

Abstract: Management of controls in a graphical user interface (GUI) of a computer system. In one aspect, a command is received to create and display a window in the GUI, the window including one or more controls, each control operative to perform a function of an application in response to selection. An associated scope for each control is determined and indicates an extent of shared use of the control within the GUI. It is determined if a different instance of the control already exists within the scope for the control. If so, resources of the different instance are referenced to be shared for use with the control and new resources are not created for the control. If no different instance exists within the scope, new resources for the control are created and stored. The window and the controls in the GUI are displayed.

Abstract: A method is provided to use a Smith Chart technique to obtain frequency domain network performance information corresponding to a passive network including one or more passive devices comprising: receiving first data representing a first Smith Chart plot of coefficients representing measured mismatch between a source impedance of a network and a load impedance of the network for higher frequency components; and extrapolating a predicted substantially spiral shaped second Smith Chart plot of coefficients based upon the first data, which includes a coefficient representing predicted mismatch between the source impedance of the network and the load impedance of the network for lower frequency components.

Abstract: The present approach is directed to an improved method, system, and computer program product for visually presenting layout options for generating an electronic design. The visual presentation could be employed to display a set of layout choices when correcting errors or rules violations identified in the design. Alternatively, the visual presentation could be employed to display layout choices during the initial design entry phase for the electronic design.

Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.

Abstract: Method and apparatus for implementing communication between a software side and a hardware side of a test bench in a transaction-based acceleration verification system are described. In one example, transactors and communication channels are identified in a hierarchy of the test bench. Software side endpoints of the communication channels are automatically bound to hardware side endpoints of the communication channels during verification based on naming attributes of the transactors and communication channels with respect to the software side and the hardware side of the test bench.

Abstract: Systems and methods to enable a user to edit subMaster content of selected instances of an electronic layout design, including editing the contents of selected instances of an existing subMaster of an EDA design, generating a new subMaster to incorporate the modified contents of the selected instances, and binding the new subMaster to the selected instances without losing the design hierarchy of the layout design.