Abstract: An apparatus and methods for the production of satisfiability reports are provided. In an exemplary embodiment, a method of producing a report is provided. The method includes generating a complete assignment for a CNF formula, deriving first second sets of clauses that are unsatisfied by the reference point, making decision assignments, performing BCP then recomputing the second set of clauses. One feature of this embodiment is that it provides for efficient solutions for SAT problems. Other embodiments provide apparatus and software products that implement the disclosed methods. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: Method and apparatus for translating a verification process having recursion for implementation in a logic emulator are described. Examples of the invention relate to a method, apparatus, and computer readable medium for translating a verification process for implementation in a hardware emulator of a logic verification system. A recursive task called by the verification process is identified. A copy of the recursive task is incorporated into the verification process. Interface registers are instantiated for the recursive task. Control flow transfer points are defined in the verification process. Calls of the recursive task are converted in the verification process to constructs for accessing the interface registers and transferring control flow among the control flow transfer points. The verification process is reorganized to describe a finite state machine (FSM) configured for implementation in the hardware emulator.

Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Abstract: In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.

Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: A method for determining a worst-case transition is disclosed. The method includes determining a plurality of output slews for the plurality of input signals based on a timing model of a gate and selecting a worst delay input signal from the plurality of input signals based on the output slews.

Abstract: A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response.

Abstract: Method and system for locating objects in a computing grid. Requests for one or more objects are received from a client or other requesting entity. A persistent object locator is distributed across the grid and searches the grid for a reference to or handle on the requested object. The persistent object locator includes an internal object locator element (IOL) that resides locally, e.g., on the client, and an external object locator element (EOL) that resides on one or more other servers that are external relative to the client. The EOL is initiated if the IOL cannot locate the requested object locally. The EOL searches the grid for the requested object and if the object is available, delivers the reference to or handle on the requested object to the requesting entity. Objects can also be registered to the POL for future use. References to objects can also be deleted from the POL in the event of a communication failure or if a server or process terminates as expected.

Abstract: Connections between digital blocks and other circuit components, such as power supplies and clocks, are verified using a discrete property or object, such as a discrete discipline. A discrete discipline is defined for each value of an operating parameter, such as voltage or clock speed, that is used in a circuit design. Each discrete discipline is propagated throughout respective nets using bottom-up and/or top-down propagation. As a result, each digital net is associated with a power supply value through its corresponding discrete discipline. A determination is made whether two digital nets are connected to each other within the same digital island. If so, a determination is made whether the digital nets are compatible. If they have conflicting discrete disciplines, then they are not compatible and an error report or signal can be generated to identify the incompatibility and its location. Compatibility checks can disregard grounded digital nets.

Abstract: Methods for analyzing circuit distortion based on contributions from separate circuit elements are presented. Local approximations that do not require high-order derivatives of device models are developed near an operating point for calculating distortion summaries including compression summaries and second-order intermodulation (IM2) distortion summaries.

Abstract: In one embodiment, a method comprises retaining at least a portion of simulation results corresponding to a first simulateable partition from a previous simulation time; and using the simulation results for a second simulateable partition (or the first simulateable partition) at a current simulation time if the second simulateable partition is equivalent to the first simulateable partition and one or more input stimuli to the second simulateable partition at the current simulation time are approximately the same as the input stimuli to the first simulateable partition at the previous simulation time. Computer accessible media storing instructions that implement the method are also contemplated.

Abstract: Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design.

Abstract: Techniques are present for designing of integrated circuits. Both custom design data and synthesized digital design data are received and merged into a design database in an automated process. The design database is then made accessible to layout tools so that the layout tools may operate upon it. These layout tools can include, but are not limited to, custom tools, digitals, or a combinations of these.

Abstract: Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.

Abstract: A circuit design process for the reduction of routing congestion is described. This process includes a block placement operation, an initial pin optimization for the block placement, and global routing based upon the initial pin optimization. Congestion data is generated from the global routing and, in an automated process, the pins are re-optimized, based upon the congestion data. This process can be used as part of a custom layout design process, for example.

Abstract: For an integrated circuit associated with a plurality of parameters whose values are described by a first probability distribution function, a method for estimating a failure probability includes selecting a first plurality of samples, performing a first test to determine an outcome for each of the first plurality of samples and identifying failed samples, and clustering the failed samples using a computer-implemented cluster forming method that, in some cases, returns multiple clusters. The method also includes forming a probability distribution function for each of the clusters, forming a composite probability distribution function that includes a weighted combination of the first probability distribution function and the probability distribution function for each of the clusters. The method further includes selecting a second plurality of samples using the composite probability distribution function and performing a second test to determine an outcome for each of the second plurality of samples.

Abstract: For an integrated circuit associated with a first plurality of parameters whose values are described by a first probability distribution function, a method for estimating a failure probability includes selecting a first plurality of samples, performing a first test to determine an outcome for each of the first plurality of samples and identifying failed samples. A second plurality of parameters is selected that has fewer parameters than the first plurality of parameters. The failed samples are clustered in the space of the second plurality of parameters using a computer-implemented cluster forming method that, in some cases, returns multiple clusters. The method also includes forming a probability distribution function for each of the clusters, forming a composite probability distribution function that includes a weighted combination of the first probability distribution function and the probability distribution function for each of the clusters.

Abstract: Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over the areas for the objects of interest with improved runtime and very good stability. These probability distributions are gradually localized to final shapes satisfying the placement constraints and optimizing an objective function.

Abstract: The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective.

Abstract: A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.