Abstract: The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element.

Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to as certain sequential optimization based design flexibility throughout multiple stages of a design flow.

Abstract: Method, apparatus, and computer readable medium for restructuring a software program hierarchy having interface files and implementation files that include the interface files are described. In one example, dependencies between program units in the interface files and the implementation files are determined. The dependencies are represented as a plurality of bit strings. Correlated bitstrings of the plurality of bit strings are clustered into a plurality of partitions. Each of the plurality of partitions is transformed into corresponding program units. New interface files are respectively created having the corresponding program units for each of the plurality of partitions.

Abstract: Disclosed are a method, system, and computer program product for implementing incremental placement for an electronic design while predicting and minimizing a perturbation impact arising from incremental placement of electronic components. In some embodiments, an initial placement of an electronic design is identified, an abstract flow is computed, target locations of various electronic components to be placed are identified, a relative ordering of electronic components is determined, and the placement is then legalized. Furthermore, in various embodiments, the method, system, or computer program product starts with an initial placement of an electronic design and derives a legal placement by using an incremental placement technique while minimizing the perturbation impact or an total quadratic movement of instances.

Abstract: A method, apparatus and method for compiling a hardware design for performing hardware emulation using synchronized processors is described. The apparatus comprises a plurality of processors defining a processor group for evaluating data regarding a hardware design and a synchronizer for synchronizing the operation of the processor group while emulating at least a portion of the hardware design. The method comprises providing a synchronization signal to a plurality of processors defining a processor group for evaluating data regarding a hardware design, receiving a ready signal from the processor group, and providing an execution signal to the processor group, where the execution signal causes the processor group to evaluate a submodel. The method for compiling the hardware design comprises converting at least one high-level construct into a sequence of operations and identifying a sequence of operations that comprise at least one conditional submodel.

Abstract: A user interface to an application processing complex data of multiple data view abstractions allows selection, placement, size and other configurable characteristics of interface components to be controlled by a user and then associated with the data abstraction and processing task. Multiple configurations may be created to simplify the interface to include only necessary controls given an abstraction level of the data view and the task on that data. The configurations may be stored using symbolic references and subsequently loaded on demand into the interface. Mechanisms may be applied to ensure that similarly referenced configurations in storage are resolved and only the desired configuration is applied.

Abstract: A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record based on one or more rules, wherein the metal fill data represents a consolidation of actual metal fill. A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record, the metal fill data representing a virtual metal fill having a configuration that is different from a configuration of actual metal fill.

Abstract: A method and apparatus for producing a verification of digital circuits is provided. In an exemplary embodiment, a set of Boolean and Integer constraints are derived, and a set of Boolean and Integer stimuli are generated that meet the constraints. These stimuli are then used to verify a digital design, and a verification report is generated. In other example embodiments, a computing apparatus and computer software product are provided. The computer software product containing a set of executable instructions that, when executed, configure the computing apparatus to produce a verification report by the provided methods.

Abstract: Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. Also, in some embodiments, selecting the wiring configuration entails defining the width and/or spacing of the routes along different directions on at least one particular wiring layer of the IC layout.

Abstract: An IC device and layout having one or more layers having route segments and at least some shield segments that are diagonal in orientation. Shield termination segments enclosing a route segment may be diagonal in orientation. Some embodiments describe a method for providing diagonal shielding for a routed net of an IC layout. A route “bloating” method is used where shield position lines (used to position the shielding) are generated by expanding out the dimensions of routes using a bloating shape. The bloating shape that may be dependent on the preferred wiring direction of the layer on which the shielding is provided. After bloating a route, a resulting bloating geometry is identified comprising the area overlapped during the expanding out of the route. The perimeter of the bloating geometry is identified comprising the shield position lines.

Abstract: Some embodiments of the invention provide a method for defining wiring directions in a design layout having several wiring layers. The method decomposes a first wiring layer into several non-overlapping regions. It assigns at least two different local preferred wiring directions to at least two of the regions. In some embodiments, the method decomposing the first wiring layer by using the vertices of items in the layout to decompose the layout. In some of these embodiments, the items include macro blocks. The method of some embodiments also identifies several power via arrays on the first wiring layer, and identifies a local preferred wiring direction based on the arrangement of the power via arrays on the first wiring layer.

Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

Abstract: A method of processing signals includes: sampling multiple signals, where each sampled signal includes multiple signal values and corresponding time values; partitioning the sampled signals into multiple partitions, where each partition includes signal values and corresponding time values for signals having identical time values within a partition time interval and where at least one additional partition is formed when two sampled signals diverge from identical time values; and saving signal values and time values from partitions in buffers corresponding to the partitions, where the buffers represent allocations of memory for saving partition values.

Abstract: In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments. A decompressor circuit receives a decompressor input and is operatively connected to the scan-segment input ends, and a compressor circuit is operatively connected to the scan segment output ends and generates a compressor output. Isolation circuits at scan-segment exits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.

Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Abstract: A method, system, and computer program product are disclosed for using pattern-dependent models at early stages of the design process. This addresses the key disadvantage of prior approaches which are restricted to using such models later in the design process for IC designs that are nearly complete. Pattern-dependent manufacturing effects are extracted from early stage designs and using the extracted pattern-dependent effects to efficiently and effectively design the integrated circuit. One or more contexts are built around one or more units of the design, with examples of units being a block or cell. The units are then used in the context to generate pattern-dependent data as a basis for one or more pattern-dependent models.

Abstract: Aspects for identifying stale contents in a file system include processing a set of attributes of each file in the file system. These aspects further also include determining access times at the directory level, recursively, from all the files in lower-level directories. The aspects further include identifying the highest-level stale directories in the file system.

Abstract: A method for reducing the order of system models exploiting sparsity is disclosed. According to one embodiment, a computer-implemented method receives a system model having a first system order. The system model contains a plurality of system nodes, a plurality of system matrices. The system nodes are reordered and a reduced order system is constructed by a matrix decomposition (e.g., Cholesky or LU decomposition) on an expansion frequency without calculating a projection matrix. The reduced order system model has a lower system order than the original system model.

Abstract: A method for connecting a programmable device (PD) and an electronic component (EC) based on a protocol, including: obtaining a signal group of the protocol having a group constraint, a first pin definition including an electrical constraint and a logical constraint, and a second pin definition; mapping the first pin definition to a first pin of the PD based on the electrical constraint, the logical constraint, and the group constraint; identifying a first pin of the EC to connect with the first pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and a connection preference; generating a first connection between the first pin of the EC and a second pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and the connection preference; and storing the first connection in an edge list.

Abstract: Embodiments of the present invention provide a virtual-view schematic editor for use in CAD systems. In response to a user request, the editor selects elements from a CAD database, determines the connectivity between the elements, and renders the elements on a single display. Virtual views may be created and stored for later re-use within the system.