Abstract: Embodiments relate to a control method, apparatus, system, device and medium for production equipment. The method includes: receiving a recipe upload instruction, and generating a first control instruction in response to the recipe upload instruction to control the production equipment to upload first recipe data; receiving the first recipe data, and parsing the first recipe data to generate a corresponding first recipe file in a preset format; generating a second control instruction during parsing the first recipe data to control the production equipment to upload second recipe data; and receiving the second recipe data, and parsing the second recipe data to generate a corresponding second recipe file in a preset format.

Abstract: A method for manufacturing semiconductor mark includes: providing a pattern having a peripheral edge corrected by Optical Proximity Correction (OPC); cutting multiple independent alignment sections from the pattern; and splicing the multiple alignment sections to form a semiconductor mark having a peripheral edge corrected by OPC.

Abstract: Embodiments of the present invention provide a storage cell and a data read/write method and storage array thereof. The storage cell includes a bit line, a tunnel junction, and four access transistors. Each access transistor includes at least an active region. The active region includes a source. The sources of the access transistors are all electrically connected to a first end of the tunnel junction. A second end of the tunnel junction is electrically connected to the bit line, and the bit line extends along a first direction. The active regions of the access transistors are isolated from one another. Long-side extension directions of the active regions of the access transistors are the same, and a first angle ? is formed between the long-side extension directions of the active regions and the first direction; wherein ? is a non-right angle.

Abstract: There is provided a package substrate and a semiconductor structure with the same. The package substrate includes a body and a plurality of conducive bridges. The body includes an opening region. The plurality of conductive bridges are disposed separately in the opening region, and adjacent conductive bridges have a respective distance value. At least two of the distance values are not equal.

Abstract: A model parameter test structure for a transistor includes: a substrate, having a first conductivity type, a plurality of isolation structures being provided in the substrate and the isolation structures being used to isolate different doped regions; a first test device, formed in the substrate and configured to obtain characteristic parameters of a source side of the transistor; and a second test device, formed in the substrate and configured to obtain characteristic parameters of a drain side of the transistor; wherein a structure of the first test device is different from a structure of the second test device.

Abstract: A control circuit includes a bias circuit. The bias circuit is configured to provide a bias current for a functional circuit. The bias circuit includes a first bias circuit and a second bias circuit. The first bias circuit is configured to provide a first bias current, and the second bias circuit is configured to provide a second bias current. Herein, the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal.

Abstract: A semiconductor device includes a substrate, first word lines and second word lines; one or more first word line trenches and one or more second word line trenches are alternately arranged on the substrate in parallel; each first word line is arranged in a respective first word line trench; each second word line is arranged in a respective second word line trench, where width of the first word line trench is greater than width of the second word line trench, and depth of the first word line trench is less than depth of the second word line trench, so that width of the first word line is greater than width of the second word line, height of the first word line is less than height of the second word line, and threshold voltage of the first word line is greater than threshold voltage of the second word line.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; patterning the substrate to form a substrate layer and a plurality of silicon pillars; forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars; forming an isolation structure on the oxide layer, gaps being provided between upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gaps; partially removing the isolation structure and retaining the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars.

Abstract: A method for measuring an element concentration of a material includes: a material sample is irradiated with first electromagnetic waves; second electromagnetic waves radiated by the material sample are obtained under the action of the first electromagnetic waves; material property parameters of the material sample are determined by detecting the second electromagnetic waves; and an element concentration of the material sample is determined according to the material property parameters.

Abstract: An impedance calibration circuit including: a calibration circuit configured to receive a first calibration clock signal, to perform impedance calibration on a basis of the first calibration clock signal, and to output a first stop signal when the calibration is completed; a first detection circuit configured to detect calibration time of the impedance calibration circuit, and to output a second stop signal when the calibration time reaches a preset value; and a calibration control circuit configured to receive the first stop signal and the second stop signal and to output the first calibration clock signal. When the first stop signal or the second stop signal is received, the calibration control circuit stops outputting the first calibration clock signal.

Abstract: A buried wordline structure fabrication method includes: providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom; performing epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench; and forming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure.

Abstract: The present disclosure provides a semiconductor device, a method of manufacturing a semiconductor device and an electronic device. The method of manufacturing a semiconductor device includes: forming word line trenches on a semiconductor substrate, forming a word line structure in each of the word line trenches, and finally forming active regions. The word line trenches pass through the semiconductor substrate without passing through other material.

Abstract: Embodiments of the present application provide a squeezing device, a photoresist supply system, and a photoresist supply method. The squeezing device includes: a base, configured to bear a photoresist bottle; a support rail, vertically arranged on the base; a squeezing structure, an end of the squeezing structure is movably arranged on the support rail so that the squeezing structure moves up and down along the rail direction of the support rail; and a driving module, configured to drive the squeezing structure to deform the squeezing structure so as to reduce the area of a region enclosed by the squeezing structure, and also configured to drive the deformed squeezing structure so that the squeezing structure moves up and down along the rail direction of the support rail. By squeezing the photoresist bottle by the squeezing device, the utilization rate of the photoresist in the photoresist bottle is improved.

Abstract: Embodiments of the present disclosure relate to an address selection circuit and a control method thereof, and a memory. The address selection circuit includes an address receiving circuit, a row hammer address generation circuit, and a decoding circuit. The address receiving circuit is configured to output a first address output signal in response to a first selection signal, where the first address output signal includes a received regular refresh address signal or an active address signal. The row hammer address generation circuit is configured to: generate a second address output signal and a row hammer address redundancy identifier according to the first selection signal, an actual active address signal, and the first address output signal. The decoding circuit is configured to: generate a target address and the actual active address signal according to the second address output signal and the row hammer address redundancy identifier.

Abstract: An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a laminate structure arranged on the substrate and including first semiconductor layers spaced apart from each other in a direction perpendicular to a top surface of the substrate, each first semiconductor layer including channel areas spaced apart from each other in a first direction, and first doped areas and second doped areas, each first doped area being arranged on one side of a respective one of the channel areas in a second direction, each second doped area being arranged on another side of the respective one of the channel areas in the second direction; and a word line structure including word lines extending in the first direction, an edge of each word line being flush with an edge of a respective one of the channel areas in the second direction.

Abstract: An address signal transmission circuit includes a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, where the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal; and a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, where the selection circuit inverts the second address signal to obtain the address inverted signal.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple initial active pillars on the substrate; forming a gate layer between initial active pillars; and forming a first dielectric layer with openings on the gate layer and on the initial active pillars; removing part of the initial active pillar located in each opening to form an active pillar; and removing part of the gate layer to form an isolation trench and a word line, such that two adjacent active pillars in the same row are located on two sides of the isolation trench.

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate; forming a first wordline trench structure; forming a first sacrificial layer at the bottom of the first wordline trench structure; filling the first wordline trench structure located in active regions by epitaxial growth; forming a first insulation layer covering the top of the semiconductor substrate and the first wordline trench structure; forming a second wordline trench structure and a fin-type structure in the active regions, a depth of the second wordline trench structure being less than that of the first wordline trench structure, and a projection of the second wordline trench structure in a vertical direction completely overlapping with a projection of the first sacrificial layer in the vertical direction; removing the first sacrificial layer; and filling the first wordline trench structure, the second wordline trench structure and the wordline tunnel.

Abstract: Embodiments of the present application relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged at intervals and an isolation structure located between the active regions; a word line (WL) trench, penetrating through the active region and the isolation structure along a first direction; and a WL, located in the WL trench, wherein on a section in a second direction, a first height difference is formed between the active region and the isolation structure; and the second direction is parallel to the substrate and perpendicular to the first direction.