Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.

Abstract: Embodiments of the disclosure provide a capacitance measurement method, system and apparatus, an electronic device, and a storage medium. The method is applied to a machine table and includes: obtaining a calibration file including multiple first capacitance values corresponding to a measurement probe card while the measurement probe card is floating; measuring, by the measurement probe card, multiple semiconductor devices simultaneously to obtain multiple second capacitance values corresponding to the multiple semiconductor devices, the multiple semiconductor devices being located on a same test module of a semiconductor chip; and determining target capacitance values of the multiple semiconductor devices based on the multiple first capacitance values and the multiple second capacitance values.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate; forming a first mask layer with a first pattern on the stack; forming a first photoresist layer on the first mask layer; exposing the first photoresist layer, and developing to remove the first photoresist layer on the complete die region; and etching the stack by using the first mask layer on the complete die region and the first photoresist layer on the incomplete die region as masks.

Abstract: Embodiments of the present disclosure provide a method of manufacturing a semiconductor structure. The semiconductor structure includes a peripheral area and an array area, and the method of manufacturing a semiconductor structure includes: providing a substrate; where the substrate in the peripheral area includes an active layer; a first isolation layer is further provided on the active layer; forming a buried word line in the substrate in the array area; where a second isolation layer is further provided on the buried word line; the buried word line includes a first conductive layer and a second conductive layer; patterning the first isolation layer and the second isolation layer by dry etching to form first through holes and a second through hole; where the first through holes expose a top surface of the active layer, and the second through hole exposes the second conductive layer.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a transistor; a first phase change memory structure, a bottom electrode of the first phase change memory structure being electrically connected to a first terminal (source or drain) of the transistor; a second phase change memory structure, a top electrode of the second phase change memory structure being electrically connected to the first terminal of the transistor; a first bit line, electrically connected to a top electrode of the first phase change memory structure; and a second bit line, electrically connected to a bottom electrode of the second phase change memory structure.

Abstract: The present application provides a design rule check method and apparatus, and a storage medium, which are applied to the field of chip verification. The method includes that: a DRC code file is acquired, multiple segments of DRC codes in the DRC code file are analyzed, the analyzed segments of DRC codes are classified, whether a code conflict exists in the segments of DRC codes is determined, and if the code conflict exists, a code conflict report is generated, the code conflict report being used to indicate a code position of the code conflict. By means of the method, the code error in the DRC code file can be quickly checked and positioned, assisting a tester in modifying a DRM file and the DRC file, so as to improve the execution efficiency of the DRC code, and meanwhile, shorten the time for DRC development.

Abstract: Provided is a packaging method, including: providing a base with a groove in its surface, which includes at least one pad exposed by the groove; providing a chip having a first surface and a second surface opposite to each other, at least one conductive bump being provided on the first surface of the chip; filling a first binder in the groove; applying a second binder on the first surface of the chip and the conductive bump; and installing the chip on the base, the conductive bump passing through the first binder and the second binder to connect with the pad.

Abstract: A counter circuit includes multiple stages of counting circuits corresponding to binary bits, each stage being configured to: obtain a carry signal and a this-time bit value according to an addend signal and a bit value currently output by the stage, output the carry signal to a next-stage counting circuit, latch the this-time bit value in response to a first clock and output same to an output terminal of the stage of counting circuit in response to a second clock. An output of the counter circuit is composed of bit values output by the multiple stages and is a binary representation of a counting result. An addend signal of a start-stage counting circuit is a high-level signal and an addend signal of a non-start-stage counting circuit is a carry signal output by an immediately previous stage. The first and second clocks are obtained based on division of a system clock.

Abstract: A method for manufacturing a buried word line transistor can include the following operations. A semiconductor substrate having an active region is provided. A first trench is formed in the active region. A first insulation layer is formed on a side wall of the first trench. A bottom portion of the first trench is etched to form a second trench. A gate oxide layer is formed on a side wall of the first insulation layer and a bottom portion and a side wall of the second trench. A barrier layer is formed at a bottom portion and portion of a side wall of the gate oxide layer. A metal filler layer is formed on an inner side of the barrier layer. The first insulation layer is removed to form a side trench. A second insulation layer is formed at a top end of the side trench. A sealed air spacer layer is formed.

Abstract: The present application provides a semiconductor device, which includes a shallow trench isolation structure, located in a substrate, and comprises a first region and a second region alternately arranged. The width of the first region is greater than the width of the second region. A first filling layer and a second filling layer are sequentially arranged in the first region, and a first filling layer is arranged in the second region; wherein, in the first region, the height of the first filling layer is lower than the height of the second filling layer. The device provides an advantage that the saddle-shaped shallow trench isolation structure in the first region reduces the trapping centers during any interference from adjacent word line structures, and also reduces the overlap areas of adjacent word line structures formed subsequently, thereby reducing parasitic capacitance, curtailing leakage and improving the semiconductor device's performance.

Abstract: A method for forming a capacitor, the capacitor and a semiconductor device are provided. The method includes: providing a semiconductor structure including a substrate, a stacked-layer structure, a protective layer, a first mask layer, and a photolithography layer which is provided with a plurality of cross-shaped patterns arranged in a square close-packed manner; patterning the first mask layer based on the photolithography layer; forming a plurality of through holes penetrating through the protective layer and the stacked-layer structure based on the patterned first mask layer by etching, in which in a direction perpendicular to a surface of the substrate, a projection of each through hole is cross-shaped, and the plurality of through holes are arranged in the square close-packed manner; and forming a first electrode layer, a dielectric layer and a second electrode layer covering an inner wall of each through hole to form the capacitor.

Abstract: A semiconductor structure and a method for same are provided. The semiconductor structure includes: a first base having a first face, a second base having a second face, and a welding structure. The first base has an electrical connection column protruding from the first face. A first groove is provided at top of the electrical connection column. A conductive column is provided in the second base, and the second base also has a second groove. A top face and at least portion of a side face of the conductive column are exposed by the second groove. The electrical connection column is partially located in the second groove, and the conductive column is partially located in the first groove. At least portion of the welding structure is filled in the second groove, and at least further portion of the welding structure is filled between the conductive column and first groove.

Abstract: The embodiments of the disclosure provide a method and device for generating a command sequence, a method and device for testing, and a storage medium. The method for generating a command sequence includes that: at least one executable CMD is determined based on a state machine module according to a current state; a command weight corresponding to the at least one executable CMD is acquired, and a random command is generated from the at least one executable CMD by taking the command weight as a constraint condition; and a next state is determined based on the state machine module according to the random command, and the next state is taken as the current state to continuously execute the step of determining at least one executable CMD based on the state machine module according to the current state, to generate a random command sequence.

Abstract: A semiconductor device, including: a substrate; a gate oxide layer located in or on the substrate; and a gate located on a surface of the gate oxide layer, the gate including a monocrystalline silicon layer.

Abstract: Embodiments of the present disclosure include a layout of a semiconductor structure, including: a column decoder, wherein the column decoder includes a first P-type transistor region, a second P-type transistor region, a first N-type transistor region, a second N-type transistor region, and a NAND gate region. The first P-type transistor region is located above the first N-type transistor region, the second P-type transistor region is located above the first P-type transistor region, and the second N-type transistor region is located above the second P-type transistor region; the NAND gate region is adjacent to the first P-type transistor region, the second P-type transistor region, and the first N-type transistor region.

Abstract: A semiconductor structure includes: a pad structure disposed above a substrate; and a capacitor structure which is disposed between the substrate and the pad structure, is arranged to be opposite to the pad structure, and includes at least two capacitor units connected in parallel and spaced apart from each other, each of the capacitor units includes at least one capacitor device.

Abstract: The present application relates to a preparation method for leads of semiconductor structure and semiconductor structure. The preparation method comprises: providing a substrate covered with a conductive layer, the substrate having a first region and a second region being connected with the first region at side surfaces; sequentially forming, on the conductive layer, a second dielectric layer, a first dielectric layer and a mask layer which are superposed one upon the other; etching the second dielectric layer for the first time; removing the mask layer in the first region; etching the second dielectric layer for the second time, forming, respectively in the first region and the second region, a first window and a second window; and etching the exposed conductive layer, forming leads comprising wide lines in the first region and narrow lines in the second region.

Abstract: The present disclosure provides a semiconductor manufacturing process control method and apparatus, a device, and a storage medium. The method includes: analyzing wafer lot information and determining a current product lot of a current product; obtaining historical measurement data within a specified period; when determining that the historical measurement data does not include first measurement data of the current product lot, if determining, based on preset configuration information, that the historical measurement data includes second measurement data of a target product lot, determining a target regulatory data based on the preset configuration information and the second measurement data; and controlling a production parameter of the current product based on the target regulatory data.

Abstract: A method for forming the conductive layer includes: providing a first conductive film and a solution with a conductive material; coating a surface of the first conductive film with the solution, before performing the coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; and in a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, wherein the second conductive film including the conductive material.

Abstract: Provided are a semiconductor structure and a method for manufacturing the same. The method for manufacturing a semiconductor structure includes that a substrate is provided, and a first structure is formed on the substrate; a first supporting layer is formed, the first supporting layer covering the first structure; a second supporting layer is formed, the second supporting layer covering the first supporting layer; and the first supporting layer and the second supporting layer on an upper surface of the first structure, and the first supporting layer between the first structure and the second supporting layer are removed, a top surface of the second supporting layer being higher than the top surface of the first structure.