Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
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Patent number: 11930633Abstract: A method for preparing a semiconductor device, including providing a substrate, where a word line structure is formed in the substrate; a bit line supporting layer includes a first oxide layer and a first nitride layer. A bit line structure is formed in the first nitride layer, and the first oxide layer is formed on both sides of the bit line structure and located in the first nitride layer; patterning the supporting structure to form a first via corresponding to the bit line structure; and etching the bit line supporting layer to a preset height along the first via, adjusting an etching parameter and a selective etching ratio of etching gas for an oxide layer to a nitride layer, and continuing to etch the bit line supporting layer until the bit line structure is exposed, to form a polymer layer above the bit line structure.Type: GrantFiled: August 13, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yule Sun
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Patent number: 11930630Abstract: A Dynamic Random Access Memory (DRAM) capacitor and a preparation method therefor are provided. The DRAM capacitor includes a dielectric layer, and the dielectric layer includes a high dielectric material layer, and low dielectric loss material layers provided on both side surfaces of the high dielectric material layer.Type: GrantFiled: September 10, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Zhuo Chen, Ying-Chih Wang, Shih-Shin Wang
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Patent number: 11927620Abstract: Provided is a method for simulating electricity of a wafer chip. The method includes: a database is constructed, the database including spectroscopic data of a semiconductor structure of the wafer chip obtained from a target key process, actual electrical data of the wafer chip, and a correspondence between the spectroscopic data and the actual electrical data; the target key process is performed on a target wafer chip to obtain the spectroscopic data of the semiconductor structure of the target wafer chip obtained from the target key process, the spectroscopic data being target spectroscopic data; the electrical data of the target wafer chip is simulated based on the obtained target spectroscopic data and the database, the electrical data being target electrical data.Type: GrantFiled: September 17, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Hongxiang Li, Shih-Shin Wang
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Patent number: 11928341Abstract: The disclosure relates to a sleep control method and a sleep control circuit, a data transmission circuit includes at least two data transmission structures, each includes a storage transmission end, a bus transmission end, and an interactive transmission end, the storage transmission end is connected to a storage area, the bus transmission end is connected to a data bus, and the interactive transmission end is connected to another data transmission structure; the method includes: in a sleep stage, sleep data is transmitted to the data bus; the bus transmission end and the storage transmission end are turned on, a sending terminal of the interactive transmission end is turned on, and a receiving terminal of the interactive transmission end is turned off, so that data input from the bus transmission end is output through the storage transmission end and the interactive transmission end.Type: GrantFiled: June 27, 2022Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yufeng Tao
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Patent number: 11927544Abstract: Provided are a wafer defect tracing method and apparatus, an electronic device and a computer readable medium. The method includes: obtaining defect data of a wafer; obtaining position data of fail bits of the wafer; determining a defect area of a storage block in the wafer according to the defect data; determining a fail bit count of the storage block in the wafer according to the position data of the fail bits; processing the defect area and the fail bit count of each storage block in the wafer, so as to obtain a correlation coefficient; and determining an abnormal reason for the fail bits of the wafer according to the correlation coefficient.Type: GrantFiled: September 15, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yui-Lang Chen
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Patent number: 11929137Abstract: The present application provides a method for testing a memory, including the steps of: providing a database, the database including a deviation value between a data strobe signal and a clock signal and a corresponding relationship between the deviation value and a memory parameter; searching the database for a deviation value corresponding to a preset memory parameter when a read command is applied to the memory under the preset memory parameter; acquiring a time value at which an output signal is to be captured according to the deviation value; and capturing the output signal at the time value to perform the testing for the memory.Type: GrantFiled: November 17, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yangyang Dai
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Patent number: 11929282Abstract: The method for preparing the semiconductor structure includes: providing a substrate; successively arranging a first conductive material layer, a barrier material layer, a second conductive material layer and a first dielectric material layer on the substrate stacked onto one another; forming a supporting layer on the first dielectric material layer, in which the supporting layer includes a plurality of supporting pattern structures spaced apart from each other, and a first trench is provided between two adjacent supporting pattern structures; forming a second dielectric layer, in which the second dielectric layer fills the first trench; etching the second dielectric layer, the first dielectric material layer, the second conductive material layer, the barrier material layer and the first conductive material layer to form a bit line array; and forming a bit line protective layer.Type: GrantFiled: September 20, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Zhaopei Cui, Jingwen Lu
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Patent number: 11929112Abstract: The sense amplifier includes: an amplification module configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage; a first switch module configured to control the amplification module to be disconnected from the reference bit line, when the sense amplifier performs a read operation for the bit line and is at the amplification stage. In the disclosure, the power consumption of the sense amplifier may be reduced.Type: GrantFiled: September 13, 2021Date of Patent: March 12, 2024Assignees: ANHUI UNIVERSITY, CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Chunyu Peng, Zijian Wang, Wenjuan Lu, Xiulong Wu, Jun He, Xin Li, Zhan Ying, Kanyu Cao, Zhiting Lin, Junning Chen
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Patent number: 11929716Abstract: The disclosure provides a Sense Amplifier (SA), a memory and a method for controlling the SA, and relates to the technical field of semiconductor memories. The SA includes: an amplifier module; an offset voltage storage unit electrically connected to the amplifier module and configured to store an offset voltage of the amplifier module in an offset elimination stage of the SA; and a load compensation unit electrically connected to the amplifier module and configured to compensate a difference between loads of the amplifier module in an amplification stage of the SA. The disclosure may improve an accuracy of reading data of the SA.Type: GrantFiled: September 13, 2021Date of Patent: March 12, 2024Assignees: ANHUI UNIVERSITY, CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Xiulong Wu, Li Zhao, Yangkuo Zhao, Jun He, Xin Li, Zhan Ying, Kanyu Cao, Wenjuan Lu, Chunyu Peng, Zhiting Lin, Junning Chen
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Patent number: 11929610Abstract: Embodiments provide an electrostatic discharge (ESD) protection circuit and an electrostatic discharge method. The ESD protection circuit includes: a pulse detection unit (100), a discharge transistor (300), a feedback delay unit (200), and a processing unit (400). A first terminal of the pulse detection unit (100) is connected to a first pad (101), a second terminal of the pulse detection unit (100) is connected to a second pad (102), and an output terminal of the pulse detection unit (100) is configured to output a detection result signal. A gate of the discharge transistor (300) is connected to the output terminal of the pulse detection unit (100), a drain of the discharge transistor (300) is connected to the first pad (101), and a source of the discharge transistor (300) is connected to the second pad (102). The feedback delay unit (200) includes a PMOS transistor (Mp) and an NMOS transistor (Mn).Type: GrantFiled: September 2, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Qian Xu
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Patent number: 11929132Abstract: The present invention relates to a testing method, a testing system, and a testing apparatus for a semiconductor chip. The method includes: acquiring a target chip; obtaining an abnormal chip after a test of read and write functions is performed separately on a preset number of memory cells in an edge region of the target chip; recording location information of individual memory cells with abnormal read and write functions on the abnormal chip; judging whether an abnormality of read and write functions of the abnormal chip is a block abnormality based on the location information; wherein the abnormal chip refers to the target chip including the memory cell with abnormal read and write functions.Type: GrantFiled: June 16, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Cheng-Jer Yang
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Patent number: 11929255Abstract: Provided is a method of high-density pattern forming, which includes: providing a substrate; forming a hard mask layer on the substrate; forming a sacrificial layer on the hard mask layer; forming photoresists arranged at intervals on the sacrificial layer; etching the sacrificial layer to enable the sacrificial layer to form a mandrel corresponding to the photoresist one by one, wherein a cross-sectional size of the mandrel gradually decreases from an end of the mandrel away from the hard mask layer to an end close to the hard mask layer; forming an isolation layer on the mandrel; removing the isolation layer on the top of the mandrel, the isolation layer covering the hard mask layer, and the mandrel to form an isolation sidewall pattern; and transferring the isolation sidewall pattern to the hard mask layer.Type: GrantFiled: May 25, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Chen En Wu
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Patent number: 11929350Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and filling an insulating dielectric in a gap between a sidewall of the groove and the semiconductor die stack to form an insulating dielectric layer covering an upper surface of the semiconductor die stack to seal up the semiconductor die stack so as to form the semiconductor package structure.Type: GrantFiled: July 12, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jie Liu, Zhan Ying
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Patent number: 11927526Abstract: A device detection method and system are provided. The method includes: acquiring first spectral intensity graphs for predetermined regions in the cavity of the target device; acquiring second spectral intensity graphs for the predetermined regions when the target device has finished N processing tasks, where N is a natural number; and detecting the cleanliness in the cavity of the target device according to the first spectral intensity graphs and the second spectral intensity graphs.Type: GrantFiled: October 28, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Ben Wang
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Patent number: 11928948Abstract: A method for monitoring environmental data and a monitoring system are provided. The method includes that: a second server receives first environmental data from a first server; the second server determines that data loss occurs in the first environmental data; the second server obtains lost data in the first environmental data from the first server; the second server obtains second environmental data according to the first environmental data and the lost data; and responsive to a concentration of a sampled gas in the second environmental data exceeding a preset concentration threshold, the second server sends warning information to a terminal device.Type: GrantFiled: January 20, 2022Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yunxiao Ding, Xiaohui Liu
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Patent number: 11930644Abstract: The present disclosure provides a semiconductor structure and a storage circuit that implements the storage structure of a magnetoresistive random access memory (MRAM) based on a dynamic random access memory (DRAM) fabrication platform.Type: GrantFiled: August 3, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Er-Xuan Ping, Xiaoguang Wang, Baolei Wu, Yulei Wu
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Patent number: 11929280Abstract: A contact window structure and a method for forming the contact window structure are provided. The method includes: an etching spacer is formed on a surface of a target layer, and a dielectric layer covering a substrate, the target layer and the etching spacer is formed; the dielectric layer is etched to form an etching hole in the dielectric layer, a bottom of the etching hole exposing a top surface of the etching spacer; and the etching spacer is removed along the etching hole to form an etching channel communicating with the etching hole, the etching channel exposing a portion of the surface of the target layer and constituting a contact window structure with the etching hole.Type: GrantFiled: August 9, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Ping-Heng Wu
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Patent number: 11929130Abstract: The present disclosure relates to the field of integrated circuit technologies, and provides a method and device for testing an SR cycle as well as a method and device for testing an AR number. The method for testing an SR cycle includes: executing a preset number of data-retention-capacity acquisition steps, the data-retention-capacity acquisition step including determining a preset refresh time; sending an SR entry command to control a memory to enter an SR operation; sending an SR exit command to control the memory to exit the SR operation after the memory executes the SR for the preset refresh time; detecting a current data retention capacity of the memory; obtaining a cycle of a function of the data retention capacity with respect to the corresponding preset refresh time; and determining the SR cycle of the memory with the cycle of the function.Type: GrantFiled: January 26, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Peng Wang
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Patent number: 11930635Abstract: The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure.Type: GrantFiled: August 11, 2021Date of Patent: March 12, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Zhongming Liu, Jia Fang
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Patent number: 11929111Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module, arranged to read data in a memory cell; and a control module, electrically connected to the amplification module. In a first offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first inverter and a second inverter, and each of the first inverter and the second inverter is an inverter an input terminal and an output terminal connected to each other; and in a second offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a current mirror structure.Type: GrantFiled: September 10, 2021Date of Patent: March 12, 2024Assignees: ANHUI UNIVERSITY, CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Zhiting Lin, Guanglei Wen, Jun He, Zhan Ying, Xin Li, Kanyu Cao, Wenjuan Lu, Chunyu Peng, Xiulong Wu, Junning Chen
