Abstract: A data sampling circuit includes a first signal path and a second signal path. The first signal path is arranged to receive a first signal, process and transmit the first signal. The first signal path has a first delay, and the first delay includes a first physical delay and a compensation delay. The second signal path is arranged to receive a second signal, receive processed first signal from the first signal path, and sample the second signal according to the processed first signal.

Abstract: A test fixture includes a signal test board, a circuit routing, and a branch routing. The signal test board includes a first surface and a second surface. The first surface has a first pin and a test point. The second surface has a second pin. The circuit routing is located in the signal test board and configured to connect the first pin and a corresponding second pin. A portion of the circuit routing includes an upper routing connected with one first pin, a lower routing connected with one second pin, and a via-hole routing connected with two ends of the upper routing and the lower routing. One end, connected with the via-hole routing, of the upper routing is located in a projection area of the corresponding test point. The branch routing is located in the signal test board and configured to connect the test point with a corresponding upper routing.

Abstract: A discharge unit is connected to a power pad, a ground pad, and an I/O pad, and can discharge an electrostatic charge when an electrostatic pulse appears on any of the power pad, the ground pad, and the I/O pad. The discharge unit includes a first discharge unit and a second discharge unit, the first discharge unit is connected to the second discharge unit, the power pad, and the I/O pad, and the second discharge unit is connected to the ground pad and the I/O pad. The first discharge unit and/or the second discharge unit can discharge electrostatic charges on different pads, respectively.

Abstract: A memory includes a storage circuit, a first reading circuit, a second reading circuit, and a plurality of correcting circuits. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays. The sense amplifier arrays and the storage unit arrays are arranged alternately, and the sense amplifier arrays are configured to perform data reading and writing on the storage unit arrays. The first reading circuit is configured to compare a reference voltage signal with a signal on a first data line corresponding to the first reading circuit, and output a comparison result as read-out data. The second reading circuit is configured to compare the reference voltage signal with a signal on a first data line corresponding to the second reading circuit, and output a comparison result as read-out data.

Abstract: A protection circuit can be applied in a chip, and include: a first protection unit and a first element to be protected, wherein the first protection unit is configured to receive a first input signal and a control signal, and is configured to output a first output signal, the first element to be protected includes a first P-type transistor, and a gate of the P-type transistor is configured to receive the first output signal. When the chip enters a burn-in test, the first output signal is a high-level signal.

Abstract: A signal generation circuit includes: a clock module, configured to generate a clock signal based on a flag signal; a control module, configured to generate a control signal according to number of transitions of the clock signal within a fixed time; and a generation module, respectively connected to the clock module and the control module, and configured to receive the clock signal, the control signal, and the flag signal, and to generate a target signal. When the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level. After being maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level. The generation module is further configured to determine the target duration according to the clock signal and the control signal.

Abstract: A test method for an alignment error includes: providing a substrate, wherein a first conductive layer and a second conductive layer are arranged on the substrate at intervals, and the first conductive layer and the second conductive layer are arranged in a first direction; acquiring a first distance; acquiring a first resistance of the first conductive layer and a second resistance of the second conductive layer; acquiring an actual distance between the first conductive layer and the second conductive layer according to the first distance, the first resistance, and the second resistance; and acquiring a value of the alignment error between the first conductive layer and the second conductive layer based on the actual distance and a standard distance between the first conductive layer and the second conductive layer.

Abstract: Disclosed in the present disclosure are a cleaning machine and a cleaning method. The cleaning machine includes: a wet cleaning module, configured to execute a wet cleaning process on a wafer; a dry cleaning module, configured to execute a dry cleaning process on the wafer; a conveying module, configured to input the wafer into the wet cleaning module or the dry cleaning module, or output the wafer from the wet cleaning module or the dry cleaning module; a transferring module, configured to transfer the wafer from the wet cleaning module to the dry cleaning module or transfer the wafer from the dry cleaning module to the wet cleaning module; and a processing module, configured to extract gas from the transferring module.

Abstract: Embodiments of the disclosure provide a comparison system including at least one comparison circuit, the comparison circuit including: a common circuit, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted; a first logical circuit, connected to the common circuit, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and a second logical circuit, connected to the common circuit, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal.

Abstract: A board adapter device includes: a first adapter structure provided with a gold finger matched with a board of a target memory module, a second adapter structure provided with a connector matched with the gold finger, and a signal transmission structure including a first and second transmission module. The first transmission module is for connecting a data signal line, a clock signal line, an address signal line, and a control signal line of the gold finger to corresponding connecting lines of the connector. The second transmission module is configured to, when receiving a power input signal, convert the power input signal into a power output signal matched with a power supply of the target memory module, and transmit the power output signal to a power signal line of the connector.

Abstract: A gate valve device includes a cleaning component, a first lifting component, and a second lifting component. The cleaning component is arranged on the second lifting component. The first lifting component is configured to control whether an opening on a side of a vacuum chamber close to a swing gate valve is in a closed state. The second lifting component is configured to, in a case that the opening on the side of the vacuum chamber close to the swing gate valve is in the closed state, control the cleaning component to clean the swing gate valve.

Abstract: A posture adjustment device for an optical sensor includes: a controller, a posture detector, and a posture adjustment structure. An optical sensor to be detected is fixed on the posture adjustment structure. The posture detector receives an emitted beam of the optical sensor to be detected, detects a posture of the optical sensor to be detected according to the emitted beam, and sends posture information to the controller. The controller controls, according to the posture information, the posture adjustment structure to adjust the posture of the optical sensor to be detected.

Abstract: A method of forming a semiconductor structure includes: a substrate is provided, the substrate at least comprising a conducting layer; a bottom supporting layer and a stacking structure being formed on a top surface of the substrate, the stacking structure including a sacrificial layer and a supporting portion that are sequentially stacked and formed; the stacking structure and the bottom supporting layer are partially etched to expose the conducting layer to form a through hole; the supporting portion of a partial width exposed from a sidewall of the through hole is laterally etched to form an air gap; a protective layer filling the air gap is formed; a lower electrode electrically connected with the conducting layer is formed on the sidewall of the through hole and a sidewall of the protective layer; the sacrificial layer is removed.

Abstract: The present disclosure provides a method and an apparatus for testing a memory chip, and a storage medium, and belongs to the technical field of semiconductors. The method for testing a memory chip includes: writing test data into a memory cell of a to-be-tested memory chip; reading stored data from the memory cell; and generating a test result of the to-be-tested memory chip based on the test data and the stored data; wherein in the reading stored data from the memory cell, a row address strobe precharge time is less than a standard row address strobe precharge time of the to-be-tested memory chip, and/or a current sensing delay time of the to-be-tested memory chip is less than a standard sensing delay time of the to-be-tested memory chip.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.

Abstract: A method of manufacturing a semiconductor structure includes: providing a base and a dielectric layer on the base, the base in an array region being provided with discrete capacitive contact plugs and a first conductive layer being formed on a top surface of the capacitive contact plugs; sequentially forming a conversion layer and a target layer on the first conductive layer and the dielectric layer, the target layer in the array region and the first circuit region being provided with first openings through the target layer; patterning the target layer in the array region as well as in the first circuit region and the second circuit region to form a second opening and a third opening; etching the conversion layer to form a first trench; forming a filling layer filling the first trench and removing the conversion layer to form a second trench filled by a second conductive layer.

Abstract: Embodiments provide a method for sense margin detection for a sense amplifier and an electronic device. The method includes: writing first data and second data respectively to a first memory cell and a second memory cell connected to a first bit line, the first memory cell and the second memory cell being respectively connected to a first word line and a second word line adjacent to each other, and the first bit line being connected to a first sense amplifier; performing a reverse write operation on the first memory cell and the second memory cell; performing write operations on memory cells connected to the second bit line; and reading the second memory cell, and determining the preset row precharge time to be a margin value of row precharge time of the first sense amplifier when the first data is not correctly read.

Abstract: A calibration circuit includes: a differential input circuit, configured to receive first and second oscillation signals, the first and second oscillation signals having the same frequency and opposite phases, duty cycle of the first oscillation signal and duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output first and internal signals; a comparison unit, connected to an output end of the differential input circuit and configured to compare duty cycle of the first internal signal and/or duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range.

Abstract: A write leveling circuit applied to a memory includes a write signal generation unit and a sampling unit. The write signal generation unit is configured to receive a first clock signal and a first indication signal, and delay a first write signal according to the first clock signal, the first indication signal and a specified bit in the first indication signal, and output a second write signal. The sampling unit is connected to the write signal generation unit, and configured to receive a first data strobe signal and the second write signal, and output a second sampling signal according to received first Data Strobe Signal (DQS) and the second write signal.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of low data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to High.