Abstract: A design method applied to a capacitor array is provided. The capacitor array includes multiple preset capacitor units, and each preset capacitor includes multiple unit capacitors. The method includes: acquiring unit simulation models of the preset capacitor units; acquiring a first simulation model of the capacitor array based on an arrangement manner of the preset capacitor units in the capacitor array and the unit simulation models of the preset capacitor unit; acquiring an arrangement direction of the preset capacitor units based on the arrangement manner, establishing a parasitic resistance equivalent test structure of a group of preset capacitor units in the same arrangement direction; obtaining a parasitic resistance of each preset capacitor unit based on the parasitic resistance equivalent test structure; and establishing a second simulation model representing the capacitor array based on the parasitic resistance of each preset capacitor unit and the first simulation model.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. According to embodiments of the present disclosure, a height of the work function layer, especially a height of the second portion of the work function layer, is significantly increased, and a height of the first gate material layer is significantly reduced, so that the height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is maintained at 3 to 8:1 to 1.5:1; therefore, it can be ensured that the work function of the WL groove filling material layer of the recessed gate structure with a small WL width will be significantly increased, thereby greatly weakening the row hammer effect at the bottom of the WL groove and obviously reducing the GIDL effect at the upper part of the WL groove.

Abstract: Provided are a memory detection method, a computer device and a storage medium. The method includes: initializing all storage units in a storage unit array; determining a plurality of target wordlines, two adjacent target wordlines being provided with a plurality of interfering wordlines therebetween; turning on the target wordlines, and performing a write operation on storage units connected to the target wordlines; performing repeatedly turn-on and turn-off of the interfering wordlines for a plurality of times; and performing a read operation on the storage units connected to the target wordlines. A write operation is performed on the storage units connected to the interfering wordlines by means of forced current sinking.

Abstract: Embodiments of this application provide a method and system for adjusting a memory, and a semiconductor device. The method for adjusting a memory includes: acquiring a mapping relationship among a temperature of a transistor, a substrate bias voltage of a sense amplification transistor in a sense amplifier, and an actual data writing time of the memory; acquiring a current temperature of the transistor; and adjusting the substrate bias voltage on the basis of the current temperature and the mapping relationship, such that an actual data writing time corresponding to an adjusted substrate bias voltage is within a preset writing time.

Abstract: The present application makes public a magnetic memory and a reading/writing method thereof, which magnetic memory comprises at least one cell layer, and the cell layer includes a plurality of parallel second wires that are disposed in a second plane, the first plane being parallel to the second plane, and projections of the second wires onto the first plane intercrossing the first wires; a plurality of storage elements that are disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bi-directional gating components connected in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first wires, the bi-directional gating components being connected to the second wires, and the bi-directional gating components being configured to be conductive upon application of a threshold voltage and/or a threshold current.

Abstract: The disclosure provides a wafer detection method, device, apparatus, and a storage medium. The method includes: an original wafer picture to be detected is received; picture segmentation is performed on the original wafer picture to acquire a plurality of first pictures; picture zooming is performed on the original wafer picture and the first pictures to respectively acquire a second picture and a plurality of third pictures, the second picture and the third pictures meet an input size requirement of the wafer detection model to an input picture; the second picture and the third pictures are sequentially input into a wafer detection model to acquire a first detection result corresponding to the second picture and a second detection result corresponding to each third picture; and a total detection result of the original wafer picture is determined according to the first detection result and the second detection results.

Abstract: A semiconductor structure includes: a logic device including a first power line and a second power line located on a same wiring layer, extending along a first direction and arranged in parallel along a second direction, the first direction and the second direction intersecting with each other and being parallel to a plane where the wiring layer is located; and a switch driving device, the switch driving device and the logic device being arranged in parallel along the first direction, the switch driving device including a first input line and a first output line located on the same wiring layer as the first power line, extending along the first direction and arranged in parallel along the second direction, the first output line being connected with the first power line or the second power line.

Abstract: A semiconductor structure includes a substrate and a word line (WL) structure. The WL structure includes: a work function stacking structure located in the substrate, where the work function stacking structure includes multiple sequentially and alternately stacked first work function layers and second work function layers, and a work function of the first work function layer is greater than a work function of the second work function layer; a WL conductive layer located in the substrate, and located on an upper surface of the work function stacking structure; and a gate oxide layer located between the work function stacking structure and the substrate as well as between the WL conductive layer and the substrate.

Abstract: A semiconductor structure includes: a substrate; and a plurality of device structures, a plurality of bit line structures and a plurality of word line structures formed on the substrate. The device structure extends in a first direction, and the word line structure extends in a second direction, and the bit line structure extends in a third direction. The device structure includes a capacitor area and an active area. The bit line structure is electrically connected to the active areas arranged in the third direction. Herein, at least some of the bit line structures are formed with air gaps around them.

Abstract: A method for forming a capacitor array structure includes the following steps: providing a substrate, a capacitor contact being exposed on a surface of the substrate, and the substrate including an array region and a peripheral region; forming a bottom supporting layer covering the substrate and the capacitor contact, the bottom supporting layer having a gap therein; forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region; forming supporting layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; forming a capacitor hole; sequentially forming a lower electrode layer on an inner wall of the capacitor hole.

Abstract: A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.

Abstract: A read/write method includes: applying a read command to a memory device, the read command pointing to address information, reading to-be-read data from a storage cell corresponding to the address information to which the read command points, and if an error occurs in the to-be-read data, storing the address information to which the read command points in a preset storage space. The read/write operation is not performed on the address information stored in the preset storage space when the user executes the read or write operation on the memory device, which avoids a data error or data loss and greatly improves the reliability and prolongs the service life of the memory device.

Abstract: The present disclosure provides a photomask inspection system and an inspection method. The mask inspection system includes: a mask thickness measuring device having sensor modules arranged side by side for measuring the thickness of the mask; a bar code reading device; a calibration device including a calibration rod and an electromagnet, the calibration rod includes a calibration stick and a calibration base, the electromagnet is set at the bottom of the calibration base, and the calibration device calibrates the barcode reading device.

Abstract: Embodiments of the present disclosure relate to a cleaning device and a method of cleaning a nozzle, and relate to the technical field of semiconductor manufacturing. The cleaning device includes: a body configured to surround the nozzle, where the body includes a body inlet and a body outlet; and at least one row of first runners configured to introduce a cleaning agent, where the first runners are arranged along an outer circumference of the body, an outlet of each of the first runners communicates with the body, and a cleaning position is formed at the outlet of the first runner.

Abstract: This application provides a conveyor device and semiconductor production equipment, and relates to the technical field of semiconductor production equipment. The conveyor device is installed on a machine platform of semiconductor production equipment, the machine platform is provided with a guide structure, and the guide structure is provided with multiple oil injection ports arranged along an extension direction of the guide structure. The conveyor device includes a conveyor platform and a driving mechanism, where the conveyor platform is slidably installed on the guide structure to carry and convey wafers, the conveyor platform covers at least one of the multiple oil injection ports, and the driving mechanism is connected to the conveyor platform.

Abstract: A method for manufacturing a semiconductor structure includes operations as follows. A substrate is provided, and a mask layer is formed on the substrate. An etching process is performed to form a plurality of first trenches in the mask layer, where the first trench has an inverted trapezoid cross-sectional shape. An epitaxy layer is formed on the substrate, where the epitaxy layer is filled in each of the first trenches to form an active area. The mask layer is removed to form a plurality of second trenches, where the second trench is arranged between adjacent active areas, and the second trench has a regular trapezoid cross-sectional shape. A dielectric layer is filled in the second trench to form an isolation structure.

Abstract: A semiconductor structure includes a base, a chipset and a heat conduction adjusting layer. The chipset is disposed at one side of the base and includes multiple chip units arranged at intervals along a direction perpendicular to the base. Each of the chip units includes a substrate and a circuit module disposed on a surface of the substrate. The substrate includes a circuit interconnection region and a non-circuit interconnection region distributed adjacently. The circuit module is disposed on a surface of the circuit interconnection region, and adjacent chip units are electrically connected by the circuit module. The heat conduction adjusting layer is in contact with at least one of the substrates for reducing the difference of heat conduction rates between surfaces of the substrates.

Abstract: A failure analysis method includes: obtaining failure data of IO channels in a target chip particle, the target chip particle including a plurality of physical modules, a number of the plurality of physical modules is M, and each physical module including a plurality of IO channels, wherein M is a positive integer greater than or equal to 2; splitting the failure data to form M groups of module failure data corresponding to the physical modules; determining a partial failure type of each physical module according to each module failure data; and determining a storage failure type of the target chip particle according to the partial failure type of each physical module.

Abstract: The present application provides a temperature control method, an apparatus, an electronic device and a storage medium for an etching workbench. A real-time temperature of an etching workbench and a real-time temperature of a temperature control fluid are acquired firstly; then, a temperature control instruction is determined according to the real-time temperature of the etching workbench, the real-time temperature of the temperature control fluid and a limit temperature; and finally, in response to the temperature control instruction, a target operating temperature of the etching workbench is stabilized within a preset range by a circulating temperature control fluid loop.

Abstract: A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.