Abstract: A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice.

Abstract: A method for manufacturing a semiconductor package structure is disclosed. In one embodiment, the method includes the steps of forming a plurality of conductive pastes on a matrix lead frame with a groove located within a predetermined distance from each conductive paste on the lead; partially curing the conductive pastes so that the conductive pastes are in a semi-cured state; preparing at least one chip with a plurality of bumps thereon; electrically connecting the chip and the lead by implanting the bumps into the semi-cured conductive pastes, wherein the groove on the lead of the matrix lead frame is configured to receive overflowed semi-cured conductive pastes; curing the semi-cured conductive pastes to completely secure the bumped chip; and forming an encapsulating material covering the lead frame and the chip. The method can also be applied in pre-molded lead frame package.

Abstract: A conductive structure for a semiconductor integrated circuit is provided. The semiconductor integrated circuit comprises a pad, and a passivation layer partially overlapping the pad, which jointly define an opening portion. The conductive structure is adapted to be electrically connected to the pad through the opening portion. The conductive structure comprises an under bump metal (UBM). A first conductor layer formed on the under bump metal is electrically connected to the under bump metal. A second conductor layer formed on the first conductor layer and electrically connected to the first conductor layer and a cover conductor layer. Furthermore, the under bump metal, the first conductor layer, and the second conductor jointly define a basic bump structure. The cover conductor layer is adapted to cover the basic bump structure.

Abstract: A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Abstract: A method for manufacturing a semiconductor package structure is disclosed. In one embodiment, the method includes the steps of forming a plurality of conductive pastes on a matrix lead frame with a groove located within a predetermined distance from each conductive paste on the lead; partially curing the conductive pastes so that the conductive pastes are in a semi-cured state; preparing at least one chip with a plurality of bumps thereon; electrically connecting the chip and the lead by implanting the bumps into the semi-cured conductive pastes, wherein the groove on the lead of the matrix lead frame is configured to receive overflowed semi-cured conductive pastes; curing the semi-cured conductive pastes to completely secure the bumped chip; and forming an encapsulating material covering the lead frame and the chip. The method can also be applied in pre-molded lead frame package.

Abstract: A method of manufacturing a semiconductor package structure is provided. A chip is provided. An active surface of the chip is disposed on a carrier. A molding compound is formed on the carrier with a metal layer disposed thereon. The metal layer has an upper and lower surface, multiple cavities formed on the upper surface and multiple protrusions formed on the lower surface and corresponding to the cavities. The protrusions are embedded in the molding compound. The metal layer is patterned to form multiple pads on a portion of the molding compound. The carrier and the molding compound are separated. Multiple through holes are formed on the molding compound exposing the protrusions. A redistribution layer is formed on the molding compound and the active surface of the chip. Multiple solder balls are formed on the redistribution layer. A portion of the solder balls are correspondingly disposed to the pads.

Abstract: A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer.

Abstract: A chip package structure includes a chip, a flexible substrate, first leads and second leads. First bumps, second bumps and a seal ring are disposed on an active surface of the chip. The first and second bumps are respectively adjacent to first and second edges of the chip. The seal ring is located between the bumps and the edges. The chip is disposed in a chip mounting region of the flexible substrate. The first and second edges correspond to first and second sides of the chip mounting region respectively. The first leads disposed on the flexible substrate enter the chip mounting region through the first side and extend toward the second side to electrically connect the second bumps respectively. The second leads disposed on the flexible substrate enter the chip mounting region through the second side and extend toward the first side to electrically connect the first bumps respectively.

Abstract: A chip package structure includes a flexible substrate having a chip mounting region, a plurality of leads disposed on the flexible substrate, an insulating layer and a chip. Each lead includes a body portion and an inner lead portion connected to each other. The body portion is located outside the chip mounting region and has a thickness greater than that of the inner lead portion. The insulating layer is disposed on the inner lead portions. The chip has an active surface on which a plurality of bumps and a seal ring adjacent to the chip edges are disposed. The chip is mounted within the chip mounting region and electrically connects the flexible substrate by connecting the inner lead portions of the leads with the bumps. The insulating layer is corresponding to the seal ring in position when the chip is electrically connected to the flexible substrate.

Abstract: A chip package structure including a leadframe, a chip, bonding wires and an encapsulant is provided. The leadframe includes a die pad, leads and an insulating layer. The die pad includes a chip mounting portion and a periphery portion. At the periphery portion, the die pad has a second upper surface lying between a first upper surface and a lower surface of the die pad. Each lead includes a suspending portion and a terminal portion. The suspending portion connects to the terminal portion and extends from the terminal portion towards the die pad. The insulating layer is disposed on the second upper surface of the periphery portion and connects the suspending portions to the die pad. The chip is disposed on the chip mounting portion. The bonding wires electrically connect the chip to the suspending portions. The encapsulant covers the chip, the bonding wires, the insulating layer, and the leadframe.

Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.

Abstract: A chip package device includes a substrate having a chip bonding area and at least one contact pad, a chip having an active surface and an inactive surface, at least one wire, an adhesive layer, a heat dissipation element, and an encapsulation. The chip is disposed on the chip bonding area with its inactive surface facing the substrate. The chip includes at least one bonding pad disposed on the active surface. The wire correspondingly connects the at least one bonding pad and the at least one contact pad. The adhesive layer covers the active surface of the chip and encloses a portion of the wire extending over the bonding pad. The heat dissipation element is attached to the adhesive layer and covers the chip. The encapsulation partially encloses the periphery of the assembly including the chip, the adhesive and the heat dissipation element, and has an indented opening to expose the surface of the heat dissipation element.

Abstract: A thermally enhanced light emitting device package includes a substrate, a chip attached to the substrate, an encapsulant overlaid on the chip, and a plurality of non-electrically conductive carbon nanocapsules mixed in the encapsulant to facilitate heat dissipation from the chip.

Abstract: A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially covering the pad to define a first opening portion having a first lateral size. The conductive structure electrically connects to the pad via the first opening portion. The conductive structure comprises a support layer defining a second opening portion. A conductor is formed in the second opening portion to serve as a bump having a planar top surface.

Abstract: A manufacturing method of a non-leaded package structure is provided. An upper surface and a lower surface of a metal base plate are patterned so as to form a plurality of first protruding parts and at least a second protruding part on the upper surface and to form a plurality of first recess patterns on the lower surface corresponding to the first protruding parts. A first solder layer is formed in each of the first recess patterns respectively. A chip is mounted on the second protruding part and electrically connected to the first protruding parts with a plurality of bonding wires. An encapsulant is formed on the upper surface. A back etching process is performed on the lower surface to partially remove the metal base plate until the encapsulant is exposed and a lead group including at least a die pad and a plurality of leads is defined.

Abstract: A computer implemented apparatus for automatically generating and filtering creative proposals is disclosed. Particularly, the computer implemented apparatus automatically generates all possible featured component code sets which corresponding to all possible featured components, and compares them to the prior art code sets which corresponding to the prior objects. Thereby, the novel code sets which corresponding to the novel creative proposals are rapidly filtered out. The computer implemented apparatus comprises a standard component database, a permutation and combination module, a featured component code set database, a prior art code set database, a matching module, a sifting module and an output module.

Abstract: A package-on-package structure includes first and second package structures and bumps. The first package structure includes a carrier, a chip configured on the carrier, a heat spreader, and an encapsulant. The chip is electrically connected to the carrier through conductive wires. The heat spreader includes a support portion located on the chip and connection portions located respectively at two opposite sides of the support portion. The heat spreader has a circuit layer thereon, covers the chip and the conductive wires, and electrically connects the carrier through the circuit layer on the connecting portions. The encapsulant encapsulates the chip, the conductive wires, a portion of the heat spreader, and a portion of the carrier. The bumps are configured on the support portion. The second package structure is configured on the first package structure and is electrically connected to the first package structure through the bumps.

Abstract: A chip bump structure is formed on a substrate. The substrate includes at least one contact pad and a dielectric layer. The dielectric layer has at least one opening. The at least one opening exposes the at least one contact pad. The chip bump structure includes at least one elastic bump, at least one first metal layer, at least one second metal layer, and at least one solder ball. The at least one elastic bump covers a central portion of the at least one contact pad. The at least one first metal layer covers the at least one elastic bump. The at least one first metal layer has a portion of the at least one contact pad. The portion of the at least one contact pad is not overlaid by the at least one elastic bump. The at least one second metal layer is formed on a portion of the at least one first metal layer. The portion of the at least one first metal layer is located on the top of the at least one elastic bump. The at least one solder ball is formed on the at least one second metal layer.

Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.