Abstract: A method and apparatus are disclosed for attenuating RF noise produced by electronic systems by providing low RF impedance shorting of heat dissipating structures, such as heat sinks, to PCB reference planes. The RF impedance shorting path uses existing package pins with dedicated electrical paths through the package to the bottom surface of the heat sink. Such an arrangement provides very low RF impedance because of the minimal length and resistance of the shorting path, and also provides minimal disruption of the PCB design rules and tolerances by using existing package leads.

Abstract: A computer method and apparatus provide fast and efficient conversion (translation) of text to phonemes. The method and apparatus employ a plurality of rule sets, each formed of rules designed for specific portions of an input text string. A suffix rule set is used to match substrings from the end of an input text string to suffix rules. A prefix rule set is used to match substrings from the beginning of the input text to prefix rules. And an infix rule set is provided to match substrings taken from the middle of the input text or any remaining text not matched by either the suffix of prefix rules. Phonemic data is produced for any portion of the input text that matches a particular rule. The phonemic data may be used by a speech synthesizer to vocalize or read aloud the input text. Dictionary lookup of any portions of the input text string in conjunction with rule matching is also provided.

Abstract: The invention is a computer interface with a hardwired button array on the computer chassis for simulating the apparatus of common consumer electronic devices. Each button of the array of buttons is connected to at least two wires, with the depression of a button causing an electrical connection between the corresponding two wires. The voltage on one of these wires is forced to a steady-state logic low, while the voltage on the other wire is allowed to float electrically free. Nonetheless, the second wire is at a steady-state high voltage due to that wire's connection through a pull-up resistor to a voltage source. Upon electrical connection, the wire that is floating free acquires a logic low voltage. In response, a line state detector sends an interrupt signal to a microprocessor, which transitions the voltage on the wires forced to a steady-state logic low from a logic low to a free floating state.

Abstract: A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to memory. Arbitration and snoop logic controls access to each memory channel and maintains cache coherency. A host CPU, multimedia processor, pipes processor and display controller may independently and concurrently access memory. The pipes processor provides a decoupled input/output processor for universal serial bus and firewire serial buses to free up the host CPU.

Abstract: A computer system includes a memory device on the first data bus, a requesting device that initiates a delayed memory read transaction on a second data bus, and a bridge device that delivers the delayed memory read transaction to the first data bus and receives from the first data bus completion data requested in the memory read transaction. The bridge device includes a data storage buffer that stores the completion data, and a buffer management element that automatically requests from the memory device additional data to be placed in the data storage buffer.

Abstract: A serial bus communications method and circuitry for low speed serial bus functions. Over a two-wire communications channel, a unidirectional clock line and a bidirectional data line are used to transfer data. A protocol defines permissions, acknowledgments, terminations and retries handshaking between points. Circuitry is provided for reducing the latency of the serial bus when cooperating with the low speed functions. A resistive connection scheme is disclosed for converting high voltage signals into lower voltage signals.

Abstract: An electronic switchbox for coupling at least one internal peripheral device to any one of a plurality of computer systems. The electronic switchbox includes at least one peripheral connector for receiving and electrically coupling to an internal peripheral device, a plurality of computer connectors, each for coupling to one of the plurality of computer systems, and a selection device that selectively couples the peripheral connector to any one of the plurality of computer connectors. In this manner, at least one internal peripheral device is selectively coupled to, and thus effectively shared between, any one of the computer systems. The switchbox preferably includes a chassis with at least one slot, where the peripheral connector is mounted to the slot for receiving and electrically coupling to the internal peripheral device when plugged into the slot.

Abstract: A communication protocol detection system for enabling a network system to detect and interface one or more network devices each operating according to at least one of a plurality of different communication protocols. In one embodiment, a network interface card (NIC) is capable of operating according to one of two different communication protocols, such as the 10Base-T and 100Base-TX Ethernet Standards. The NIC includes two corresponding transceivers, where the transceivers are interfaced to a network connector for interfacing an external network device. Control logic initially enables the 10Base-T transceiver to determine if link pulses are detected. If link pulses are detected, the 100Base-T transceiver is enabled to determine if it detects the link pulses. If so, the 100Base-T transceiver is used to establish communications, and if not, the 10Base-T transceiver is used.

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.

Abstract: A method and apparatus for processing a plurality of bits stored in a memory, where the plurality of bits represent a cumulative pattern to be printed by reproducing the stored bits in a fast scan direction. Each bit stored in memory has a state (e.g., binary 0 or 1). As an example, the method selects a first subset of the plurality of bits, wherein the first subset forms a first pattern and has a center bit. Further, the method selects a second subset of the plurality of bits, wherein the second subset forms a second pattern and has a center bit coextensive with the center bit of the first subset. Next, the method determines, based on the states of the bits of the first pattern, whether the state of the center bit should be printed in the same state as it is stored in the memory. In addition, the method determines, based on the states of the bits of the second pattern, whether the state of the center bit should be printed in the same state as it is stored in the memory.

Abstract: A computer system has a communication link (e.g., a bus) and a removable circuit card that is inserted into a connector. In association with a change in the electrical state (e.g., one or more signals being disconnected or connected) between the removable circuit card and the connector, at least a portion of a predetermined communication cycle is furnished to the communication link.

Abstract: A technique is provided for selecting a preferred thread from a plurality of threads executing within a simultaneous multithreaded, out-of-order execution computer system, the preferred thread possessing those instructions which, while in flight within the pipeline of the computer system provide, in contrast to those instructions belonging to other threads, a more beneficial performance of the central processing unit of the computer system. To determine the preferred thread, a technique is provided to evaluate attributes of each thread which indicate whether the thread includes a number of instructions which are likely to be cancelled while in flight or whether a thread includes instructions which will remain in the instruction queue for a number of cycles, unable to execute, thus stalling the execution of the thread to which the instruction belongs.

Abstract: A computer system for flashing Extended System Configuration Data (ESCD) and associated variables to a flash read-only memory (ROM) is provided. During Power-On-Self-Test (POST) code, a ROM image is copied from an ESCD sector of a read-only memory to an ESCD original buffer and an ESCD write buffer. The ESCD write buffer may be updated by POST code. Following the POST operations, the contents of the ESCD write buffer are copied to an ESCD runtime buffer. The contents of the ESCD original buffer or the ESCD sector are compared to the contents of the ESCD runtime buffer. If the contents of the ESCD runtime buffer differ from the contents of the compared buffer or sector, SMI code flashes the ROM image in the ESCD runtime buffer to the flash ROM. If the ESCD runtime buffer is the same as the contents of the compared buffer or sector, a ROM flash it not performed. POST is then exited and the computer system is booted.

Abstract: A portable computer case whether in a closed state or open state permits a user to exercise control and monitor certain operating features. The user may toggle a control switch to place the computer system in a secondary operational mode, determine when a computer system is in a secondary operational mode, and adjust a digital master volume control during the secondary operational mode. The portable computer system includes a status indicator for indicating when a computer is in a secondary operational mode, digital master volume control buttons operable in a secondary operational mode, and a control switch for placing the computer system in a secondary operational mode. The status indicator, volume control buttons, and control switch are preferably provided on a top surface of the bottom shell of the portable computer for convenient access by a user.

Abstract: A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by the CPU and an ISA device to run cycles on the PCI bus is avoided. The South bridge also masks all requests to run cycles on the PCI bus that are not originated by the CPU. The South bridge includes a programmable control register and a PCI arbiter. When a control bit is set in the register, the PCI arbiter waits for FLUSHREQ to be deasserted and then masks FLUSHREQ. The PCI arbiter preferably also disables PCI arbitration by masking all non-CPU. Only the CPU can run PCI cycles when the non-CPU requests are masked. The programmable control register also includes a masking status bit that is set when both the FLUSHREQ and non-CPU request signals are masked by a request mask state machine.

Abstract: A simple and inexpensive integrated way for connecting a variety of standard computer devices, including networking integrated circuit devices, to other standard and customized integrated circuit devices, is provided as follows. An integrated circuit device has an interface, the interface is capable of transferring data from a MAC layer to a PHY layer, and also is capable of transferring data from the PHY layer to the MAC layer. There is a pin on the integrated circuit device for setting the interface in a first mode or a second mode, and when the interface is in the first mode the interface is capable of transferring signals between a MAC device and a PHY device, and when the interface is in the second mode the interface is capable of transferring signals between a first MAC device and a second MAC device.

Abstract: A bridge device for delivering data transactions between devices on two data buses in a computer system includes, for each pair of devices that may transact across the bridge device, a dedicated storage area that aids in completing transactions between the devices in the pair. The bridge device also includes a controller that allows transactions in one dedicated storage area to be completed without regard to the completion of earlier-issued transactions in another dedicated storage area.

Abstract: A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The video controller is further used for transmitting screen images to a remote computer system to facilitate system failure analysis. A plurality of system management remote units are provided for coupling to various components and busses within the host computer system.

Abstract: A technique self tests a memory system having memory modules that operate at a normal operating clock rate during a normal operating mode. Each memory module has multiple arrays of synchronous dynamic random access memory devices. The technique involves obtaining, independently of a central controller, time phase identifiers that respectively correspond to the memory modules, and reducing the normal operating clock rate to a reduced clock rate. The technique further involves executing, in the memory modules, self test transactions in different time phases depending on the obtained time phase identifiers. The memory modules initiate execution of self test transactions at the reduced clock rate. Multiple memory modules execute self test transactions in each of the different time phases. Each memory module executes self test transactions that alternately access the multiple arrays of that memory module.

Abstract: A highly parallel computer system including dual processors and dual memory controllers are coupled to an Assisted Gunning Transceiver Logic Plus (AGTL+) high speed system bus. The microprocessors are designed for a quad processor architecture requiring four processors and four connectors for the processors. To maintain signal timing and integrity in a dual processor/dual memory controller architecture, additional terminations are inserted. Printed circuit board space is conserved with a dual processor architecture. The additional connectors and traces to the additional connectors for the processors are no longer needed. Furthermore, with the dual processor design, there is no need for two additional termination cards.