Abstract: An apparatus for increasing the number of input/output ports of a computer system while maintaining the form factor of the computer chassis is disclosed. The apparatus includes a first system or motherboard mounted within the computer chassis. The first edge of a riser board is connected to the motherboard such the riser board extends generally perpendicular to the motherboard. The second edge of the riser board is connected to a second system board. The second system board is mounted to a sub panel and includes multiple input/output connectors positioned at both the front of the chassis and the rear of the chassis. A front bezel, having openings corresponding to the input/output connectors, is placed over the front of the chassis.

Abstract: In a computer system, a memory is allocated to a plurality of ports. The ports are arranged in a spatial ordering. A plurality of various sized data items are temporally ordered in each of the plurality of ports. Each data item includes a time-stamp to indicate the temporal ordering of the plurality of data items. The plurality of data items are atomically accessed by a plurality of threads using space and time coordinates. The space and time coordinates uniquely identify each of the plurality of data items.

Abstract: An adaptive interface controller including a plurality of MII ports operable at either one of the first and second transmission rates, a corresponding plurality of Manchester ports operable at the first transmission rate and an MII interface operable at the second transmission rate. The adaptive interface controller includes first select logic that provides data from an active one of the MII ports for one of the Manchester ports or to the MII interface depending upon the transmission rate. Manchester encoding logic is provided to receive data from the first select logic for an active port, to convert the data to Manchester format and to provide the encoded data to a corresponding one of the Manchester ports. Second select logic provides data transmitted to the MII interface for a selected one of the MII ports. Manchester decoding logic detects Manchester encoded data transmitted to any of the Manchester ports and converts the encoded data a serial to bit stream.

Abstract: A system and method of transferring data on a data bus is disclosed. The system includes a data bus agent having a storage medium connectable to a data bus and arranged to store data and a bus agent device adapted to receive data from the storage medium. The method includes driving a signal on a data bus by a first bus agent, sampling the signal at a second bus agent, storing the sampled signal in a storage medium associated with the second bus agent, and processing the stored signal at the second bus agent.

Abstract: To install a hard disk drive in a portable computer base housing, an upwardly opening well area is formed within the base housing and is sized to closely receive the disk drive. An electrical connector projects horizontally inwardly through one end of the well area and is operatively mateable with a corresponding connector on the front end of the disk drive. A flexible lowering strap is secured to the rear end of the disk drive. To install the disk drive, its front end is lowered into the well area while holding the strap to keep the rear end of the disk drive elevated. The strap is then used to controllably lower the balance of the disk drive into the well area to prevent installation shock to the disk drive that might occur if it were simply dropped into the well area. The lowered disk drive is then slid along the bottom of the well area to mate the well area and disk drive connectors.

Abstract: A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management logic includes control logic, a stop clock register, an alternate stop clock register, and a wakeup event register. The operating system initiates a transition to a lower power mode of operation by issuing an IDLE call to the BIOS which responds by configuring a modulation value of 15 into the alternate stop clock register. With a modulation value of 15, the SLEEPREQ signal is continuously asserted disabling the CPU's internal clock. When a subsequent wakeup event occur, an enable bit in the alternate stop clock register is cleared, disabling modulation and deasserting SLEEPREQ. In response to the wakeup event, the amount of SLEEPEQ modulation is changed. Preferably the modulation value is changed to 14 so that SLEEPREQ is asserted for 14 out of every 15 cycles of a 32 KHz clock.

Abstract: An apparatus reduces inductive coupling and cross-talks in a bus which is connected to a combination of differential devices and single-ended devices. Each differential device has a positive line and a negative line. The positive line is provided to an input of another device on a bus as normal. The negative line of the differential device is routed by a switch in accordance with the invention. The switch receives from the bus a sensing signal which is asserted when at least one single-ended device is connected to the bus. When the sensing signal is asserted, the switch grounds the negative line of the differential device. Alternatively, if all devices on the bus are differential devices, the switch connects the negative lines of the differential devices together and acts as a pass-through for the negative signal.

Abstract: A system operable with a Digital Versatile/Video Disc source, which system includes a scheme for altering one or more user preferences without interrupting the playback of a DVD title. Whereas the DVD title may have title-specific or content-provider-specific settings, the present invention decouples the user-selected preferences from the settings and stores them in a persistent medium. A generalized graphic user interface is presented for allowing a user to read the persistent medium to determine current preference values and to change them if desired. The changed values are then written back to the persistent medium so as to be available for current or future playback sessions of the DVD title. As a variation, the generalized graphic user interface may be used for providing an indication as to what other preference values are available for that title in addition to the current value in effect.

Abstract: An advanced configuration and power interface operating system transparent method to control the wake-to-sleep and sleep-to-wake transitions includes: detecting a sleep enable command; temporarily blocking completion of the sleep enable command; generating an interrupt; configuring an input-output device; and completing the sleep enable command. The sleep enable command can be a write command to an advanced configuration and power interface sleep enable data storage unit. The generated interrupt can be a system management interrupt that invokes a basic input-output device configuration program.

Abstract: During start-up of an advanced configuration and power interface computer system, a resource lock value is read from nonvolatile memory. If the resource lock value indicates system resources are to be locked, possible configuration setting data associated with motherboard input-output devices, is not loaded into memory at a location known to the operating system. If the resource lock value indicates system resources are not to be locked, possible configuration setting data is loaded into memory at a location known to the operating system.

Abstract: A portable computer has a base housing to which a display housing is pivotally secured for movement between open and closed orientations. Extending across a top side opening of the base housing is a keyboard assembly which may be removed from the top side of the base housing. The removed keyboard assembly may be vertically supported on a rear portion of the base housing, to permit access to the base housing through its now exposed top side opening, by means of tabs formed on a rear side edge of the keyboard support plate structure and removably insertable in corresponding vertically extending slots in the top side wall of the base housing. This vertical support of the removed keyboard assembly prevents it from being misplaced, reduces the potential for damaging it by laying it aside on an adjacent work space area, holds the vertically supported keyboard assembly away from the display screen to prevent the keyboard assembly from scratching it.

Abstract: A computer system including a serial bus host controller and host controller driver. The host controller driver providing data structures for the host controller to operate on. The data structures having a linking mechanism for processing lists of descriptors, and alternate buffer configurations for receiving data from the serial bus devices.

Abstract: A computer system includes error handling hardware and software that logs the source of application program or system software errors before a reset occurs. Upon a catastrophic error, a retriggerable timer, which is periodically retriggered during normal system operation, instead times out causing a hardware reset. A predetermined time before this retriggerable timer times out, however, the microprocessor in the computer system is interrupted, and executes an interrupt routine in which it determines that the retriggerable timer is about to timeout, and logs the currently executing applications program or currently executing point in system software, as well as the actual location within the applications program or the system software. The reset subsequently occurs, but not before this information valuable for debugging and diagnosis is logged.

Abstract: Apparatus for supporting virtual address aliasing is disclosed in which addresses to a virtual cache are first intercepted. It is determined whether the these addresses are aliased, i.e., more than one virtual address exists for the same location in memory. If not aliased, the addresses are simply passed to the virtual cache. In the case where there is aliasing, however, dealiasing is performed. New addresses are generated and passed to the virtual cache so that the aliased addresses are directed to the same locations in the virtual cache. In this way, an operating system can be supported that uses virtual address aliasing since the CPU can transparently issue aliased virtual addresses. These addresses, however, are directed to the same locations in the virtual cache so that the addresses are not aliased from the perspective of the cache, thus avoiding the need for other hardware to compensate for the aliasing. The modification, however, does not substantially impact latency.

Abstract: A method and apparatus of synchronizing a serial bus data rate to a serial bus function data rate to eliminate the build up of overruns or underruns of data. A response is provided to a start of frame packet. The response packet contains a response code for indicating a modification to the serial bus frame counter. Thereby, slight variations in data rates can be eliminated by adjusting the serial bus data rate instead of the serial bus function data rate.

Abstract: In accordance with the present invention, a method and apparatus is provided for storing victim data evicted from a cache and for satisfying pending requests or probe messages that target victim data, using a set of victim data buffers coupled to a central processing unit of a computer system. Storage locations referred to as a "victim valid bit" and a "probe valid bit" are associated with each victim data buffer in the computer system to indicate a release condition for the coupled victim data buffer. With such an arrangement, the victim data buffer can be deallocated when the victim valid bit and the probe valid bit have both been cleared.

Abstract: A data bus structure is disclosed. The structure includes a data bus having a bus agent connection point and a bus switch to selectively connect or disconnect the connection point to or from the data bus. A method of reconfiguring a data bus structure is also disclosed. The method includes providing two bus agent connection points on a data bus and a bus switch between the bus agent connection points and selecting the number of bus agent connection points on the bus by controlling the state of the bus switch.

Abstract: A method for supporting a USB-based Device Bay Controller without a hardware interface between the DBC and the 1394 bus, by intercepting 1394 GUID queries in software and returning a stored GUID which is set by the manufacturer to be correct for the hardware actually present.

Abstract: In a computerized method, the three-dimensional structure of an object is recovered from a closed-loop sequence of two-dimensional images taken by a camera undergoing some arbitrary motion. In one type of motion, the camera is held fixed, while the object completes a full 360.degree. rotation about an arbitrary axis. Alternatively, the camera can make a complete rotation about the object. In the sequence of images, feature tracking points are selected using pair-wise image registration. Ellipses are fitted to the feature tracking points to estimate the tilt of the axis of rotation. A set of variables are set to fixed values while minimizing an image-based objective function to extract a set of first structure and motion parameters. Then the set of variables freed while minimizing of the objective function continues to extract a second set of structure and motion parameters that are substantially the same as the first set of structure and motion parameters.

Abstract: An embodiment of the present invention discloses a technique that allows hot plugging a peripheral controller card, containing both a local bus and a peripheral bus on a single connector, into a host system board containing a host system bus and a host I/O bus. When mating the peripheral controller card to the host system board a local device power supply (LDPS) is inactive, a peripheral device power bus (PDPB) is powered, and signal lines of a peripheral device are maintained in a high impedance state. Following a delay after the mating, the LDPS is activated by the host operating system (OS). Following the activation of the LDPS, the host system bus is coupled to the single connector through switches that are under OS control. In response to the activation of the LDPS, the signal lines of the peripheral device are enabled.In a disclosed embodiment the peripheral controller card is a disk array controller card, the local bus is a PCI bus, and the peripheral bus is a SCSI bus.