Abstract: A memory system including a memory controller that operates in conformity with fast page mode (FPM) memory devices and an extended-data output (EDO) memory device configured to operate with the FPM memory controller by having an output enable input receiving a column address strobe (CAS) signal from the memory controller. The EDO memory device terminates its data cycle upon negation of the CAS signal, so that it operates in a similar manner as an FPM memory device. This prevents data corruption and bus cycle contention. The memory system includes a memory board coupled through a memory board connector, which receives the CAS signal from the memory controller. The memory board includes one or more module connectors, each having an output enable contact receiving the CAS signal. The EDO memory device is mounted on a memory module and includes an output enable input pin which receives the CAS signal when the memory module is plugged into the memory board.

Abstract: An assembly of a notebook computer and a docking station includes a locking apparatus for locking the computer on the station. The apparatus includes a front retaining unit attached to the station and engaged within a front recess unit in the front end portion of the computer, and a rear retaining unit attached to the station and engaged within a rear recess unit in the rear end portion of the computer. In this situation, the computer is coupled completely with a connector unit on the station. Because the front and rear end portions of the computer are locked on the station by means of the retaining units which constitute a double lock, the computer cannot be removed forcibly from the station without disengaging the retaining units from the recess units.

Abstract: By allowing a host processor to control an intelligent Peripheral Component Interface (PCI) device's reset logic, the PCI device's programmable read only memory (also known as PROM, EEPROM, or FLASH EEPROM) can be reprogrammed without storing any reprogramming instructions (also known as PROXY code) in the PROM itself. During reprogramming operations the host processor commands the PCI device into a reset-and-hold mode. During this time the host processor downloads reprogramming instructions and replacement code into the PCI's random access memory. When released from reset, the PCI device executes the reprogramming code downloaded by the host processor.

Abstract: A computer includes a packaged integrated circuit having an information storage area containing information determined only after the integrated circuit is packaged and tested, and a control circuit that uses the information to configure the computer. A computer also may include a bus line connecting two GTL electronic components at a single termination point and a pull-up resistor connecting the termination point to a termination voltage supply.

Abstract: A device causing a faulty condition in a computer system having devices is isolated by detecting for a faulty condition associated with the devices and identifying the device causing the faulty condition. The devices are coupled to a bus. The faulty condition includes a bus hang condition. The devices are turned off when a bus hang condition is detected. The devices are then turned back on to test the devices. Each device is tested by writing and reading its configuration space. Information on the bus associated with the faulty condition is stored. The stored information is retrieved after the faulty condition has occurred, with the stored information including address, data, and bus control information.

Abstract: A parallel, fault-tolerant computer system in which data is transferred between processes in a single CPU by two methods. In a first method, the data is copied each time it is transferred. In a second method, the data is not copied, but is passed through a shared memory, queueing system. The first method is used to ensure fault-tolerance and linear expandability. The second method is used to minimize the time required for inter-process communication. Use of the shared memory queueing system allows for increased vertical and horizontal modularity for processes executing in a same CPU.

Abstract: A method of theft protection for computers and computer related hardware. Warranty fraud, theft of proprietary technology, and hardware theft are minimized by encoding the hardware components such that a digitally authenticated handshake must be performed between the system and the component at power-up. If the handshake is successful, normal operation continues with all enhancements. If the handshake is unsuccessful, the device is disabled or shifted into a lower performance mode.

Abstract: A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.

Abstract: In a portable notebook computer a specially designed heat pipe-based heat exchanger assembly is used to efficiently dissipate heat from a processor board in the computer's base housing to ambient air surrounding the computer. The heat exchanger assembly includes a graphite fiber-filled outer heat exchanger body which includes a finned first portion that is exposed to the exterior of the base housing, and a second portion disposed within the base housing and thermally coupled to the processor board. The outer heat exchanger body is directly overmolded onto a thermosyphoning heat pipe having first and second longitudinal portions respectively encapsulated within the first and second outer heat exchanger portions. During computer operation, processor heat is conducted to the second heat pipe portions and is transmitted via the balance of the heat pipe to the finned outer heat exchanger portion for dissipation to ambient.

Abstract: A signal processing apparatus for processing data digital signals is disclosed. The signal processing apparatus includes a high-efficiency power switching amplifier that optimizes processing during low-power applications. A signal equalizer is further coupled to the power switching amplifier and has a plurality of signal bands for defining equalization characteristic desired for the signal processing system. A gain control unit is coupled to the signal equalizer for adjusting gain of the equalized input signal handled by the signal equalizer. Lastly, a digital amplitude compressor is coupled to the gain controller and the power switching amplifier and is programmable so as to compress only those signals having an amplitude greater than a first threshold level without compressing those signals that fall below that first threshold level. Typically, low-power applications cover wattage ranging from two to seven watts of power.

Abstract: The invention is a method and apparatus for the thermal management of computers. The method features determining a temperature of a predetermined location in the computer, reading indirect inputs of the computer, determining desired states of cooling options based on the temperature and the indirect inputs, and placing the cooling options in their desired states. To determine the desired states of the cooling options, an index is formed based on the indirect inputs; and the index indicates to which of a plurality of tables of desired states of the cooling options to refer. Alternatively, the desired states of the cooling options are determined by adjusting the value of the temperature input based on the indirect inputs; the desired states of the cooling options also are dependent on the adjusted value of the measured temperature.

Abstract: A nonintrusive monitoring system is used to determine the onset and duration times of an electrical power outage-caused down condition of a computer without requiring a pre-power outage polling of a running component of the computer and thereby degrading computer system performance. In response to a supply power outage the monitoring system switches on a battery-powered counter device, representatively a digital counter or a real time clock, and then switches the counter device back off in response to resumption of power supply to the computer. A software portion of the monitoring system then detects the count value of the counter device, and utilizes the count value to compute the onset and duration times of the previous power outage.

Abstract: An improved home location register (HLR) that includes a switch capability mediation module for implementing switch capability mediation between different mobile switching centers (MSCs). According to the invention, when one MSC (home MSC of a receiving party) attempts to communicate with another MSC (serving MSC) via the HLR serving the home MSC, the mediation module determines whether the two MSCs are provided by different vendors and whether they implement different capabilities, based on the MPCM (MSC ID Point Code Map) file records of both the originating and serving MSCs. The MPCM files store MSCs' network configuration information.

Abstract: Data errors on a communications channel in a computer system are corrected. The data is transmitted over the communications channel in a sequence of time-multiplexed phases. A storage device accumulates the phases of data. An error detector and correction device checks the accumulated data for a data error and corrects the data error. The error detection and correction device can correct a one-bit data error, a two-bit data error, and a three-bit data error. Multiple bit errors can be corrected if the multiple bits of data are transmitted over one cable wire in multiple time phases. The communications channel carries the data over N sub-channels, and a parity check generator employs a predetermined parity check matrix based upon the N sub-channels and a probability that multiple errors in the accumulated data are attributable to a faulty sub-channel that affects the same data position in different time phases of the data.

Abstract: In a computer system, an improved tool and method for debugging complex computer applications, displays the relationship between processes and resources of the processes and the contents of the stack and registers for threads of processes. Double clicking on the displayed information causes more detailed information to be displayed. The display is updated when predetermined operations are performed during debug. Debug commands are accepted by the tool through a graphical user interface using operations performed by the user directly on the graphical representation of the functions of the software application. The ability of the tool to accept user commands through the graphical user interface and to display critical debugging information using this same interface greatly facilitates debugging. The displayed information includes graphical information representing currently executing processes and their resources and further representing threads of the currently executing processes.

Abstract: A password-phrasing security mechanism utilizing personalized challenge phrasing to prompt the user into remembering a pre-defined personalized coded phrase to gain access to a secured system.

Abstract: The computer system includes a data storage device on a first data bus, a requesting device on a second data bus that initiates a request to read data from a cache line in the data storage device, beginning at a location not aligned with a first boundary of the cache line and including all remaining data in the cache line up to a second boundary. The computer system also includes a bridge device that retrieves the entire cache line from the data storage device but provides only the requested data to the requesting device.

Abstract: A technique for detecting failed batteries while the battery is attached to one or more electronic devices and is receiving a float charge is disclosed. The float voltage minimizes the normal voltage differences between battery cells. The technique employs a ratio comparative analysis of cell voltages of a battery provided across the terminals of the battery. Application of the ratio comparative analysis in assessing the condition of a battery assumes an equal voltage drop across each battery cell such that the cells are modeled as a series of resisters with respect to the float voltage. Such equal voltage drop enables a comparative ratio analysis of the voltage across each of the two portions of the battery's cell stack to the voltage across the entire battery. The comparative ratio analysis determines a voltage threshold that identifies whether a battery has a shorted or open cell.

Abstract: A method for charging nickel metal hydride and comparable batteries, in which the applied voltage is clamped to a temperature-dependent and current-dependent value which is greater than the constant voltage during most of the charging cycle, but less than any voltage at which gassing can occur.