Abstract: A method of biasing a circuit includes generating a control bias signal based on a difference between a leakage current of a baseline circuit and a reference signal; applying the control bias signal to a charge pump circuit to set a value of a reverse body bias voltage output from the charge pump, the control bias signal providing analog control of a digital clock of the charge pump circuit; and applying the reverse body bias voltage to a body of the baseline circuit.

Abstract: A programmable processing device having a control system and a programmable reference block. The control system sends digital control signals to the programmable reference block, which in turn generates analog variable signals used as reference signals for the programming of the one or more reconfigurable data converters.

Abstract: A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution.

Abstract: A semiconductor device package, a method of fabricating a semiconductor device package and a method of testing an integrated circuit utilizing a semiconductor device package are disclosed. Embodiments create a flip-flop semiconductor device package by coupling a semiconductor device, with a wire-bonded arrangement of conductive pads, in a face-up orientation beneath multiple bent leadfingers. The flip-flop package offers improved signaling properties, durability, reliability, and package density at reduced cost given that the conductive pads of the device couple directly to the bent leadfingers, without requiring the manufacture of a new device or the rerouting of signal paths. Additionally, the flip-flop configuration provides convenient means for exposing surfaces of the device (e.g., to increase heat transfer therefrom, thermal performance of the device, etc.) and/or surfaces of the leadfingers (e.g., to provide test points, wire bondouts, etc.).

Abstract: A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.

Abstract: A method in accordance with one embodiment of the invention can include receiving a request for a public key from a local node. Furthermore, the public key and a private key that corresponds to the public key can be generated. The public key can be sent to the local node. An encrypted session key can be received from the local node. The encrypted session key can be decrypted using the private key. Additionally, the decrypted session key can be sent to the local node that enables the local node to have secure wireless communication with a remote node. The remote node can generate the encrypted session key using the public key.

Abstract: A SONOS memory sensing scheme includes a reference current circuit that tracks the changes in the power supply (Vcc). An equalizer of the current sense amplifier is coupled between the read out current line and the reference current line. The current sense amplifier includes data and datab (data bar) outputs which have a common mode noise due to variations in the power supply voltage. The data output is a current generated from the memory cell, and the datab output is generated by the current reference circuit.

Abstract: A voltage protection device and method is provided to prevent accidental triggering of an silicon-controlled rectifier (SCR) unless the electrostatic discharge (ESD) is at a predefined threshold above the normal power supply operating voltage or below the ground supply operating voltage. The holding voltage upon the SCR is maintained above the threshold voltage to prevent accidental triggering. The present SCR avoids use of an additional field effect transistor (FET), and avoids relying upon the breakdown of the drain terminal of the FET, but instead programs the amount of holding voltage needed above the power supply voltage using mask-programmability, fuses, or other means for maintaining the holding voltage to a desired range above the power supply voltage. The programmed holding voltage is implemented using a barrier region between the PNP and the NPN of the PNPN junctions of the SCR.

Abstract: A circuit in accordance with one embodiment of the invention can include a variable voltage generator that is coupled to receive an input voltage. Furthermore, the circuit can include a non-volatile memory that is coupled to the variable voltage generator. The non-volatile memory can be coupled to receive programming for controlling an output voltage of the variable voltage generator.

Abstract: A memory device can include a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines independently and concurrently in synchronism with at least a first clock signal; an address port configured to receive address values on consecutive, different transitions of a second clock, each address value corresponding to an access on a different one of the data ports; and a memory array section comprising a plurality of banks, each bank providing pipelined access to storage locations therein.

Abstract: We describe an example system and method of power sharing that includes communicating a power status of each of a plurality of devices on a network to a rest of the plurality of devices connected to the network and sharing power between the plurality of devices responsive to the communicating.

Abstract: A system can include at least one power supervisor coupled between two supply voltage terminals and including a comparator circuit configured to assert at least one output signal in response to a voltage between the terminals varying from at least one trip voltage, and a memory coupled to a programming interface for storing values that establish the at least one trip voltage; and circuitry coupled between the terminals that receives the at least one output signal, and configured to hold at least a portion of the circuitry in one mode of operation in response to the assertion of at least one output signal.

Abstract: Methods and apparatus for increasing the coupling coefficient of a floating gate memory device includes an MOS capacitors with self-aligning gate structures that provide increased capacitance per unit area over conventional MOS capacitors.

Abstract: Disclosed is a dynamic detector to detect an environmental condition including a power-supply level relative to a predetermined threshold signal during a training phase; and an adjustable buffer, coupled with the dynamic detector, configured to adjust output drive strength during the training phase in response to the detected environmental condition.

Abstract: One embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element capacitively coupled with each of the first plurality of sensor elements. The second sensor element may further comprise a first main trace and a second main trace, where the first main trace and the second main trace intersect each of the first plurality of sensor elements, and where each of the main traces cross at least one of a plurality of unit cells associated with the second sensor element. The second sensor element may also comprise a connecting subtrace electrically coupled to both the first main trace and the second main trace, and within each unit cell, at least one primary subtrace branching away from the first main trace or the second main trace.

Abstract: A system comprises a temperature sensor generate multiple base-emitter voltage signals by sequentially providing various currents to a transistor, and a system controller to determine a differential voltage signal according to the multiple base-emitter voltage signals, the differential voltage signal proportional to an environmental temperature associated with the transistor.

Abstract: Embodiments described herein provide capacitance sensing devices and methods for forming such devices. The capacitance sensing devices include a substrate having a central and an outer portion. A plurality of substantially co-planar electrodes are on the central portion substrate. A first plurality of conductors are on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the outer portion of the substrate. An insulating material is coupled to the second end portions of the first plurality of conductors. A second plurality of conductors are coupled to the insulating material. Each of the second plurality of conductors is electrically connected to the second end portion of at least some of the first plurality of conductors and is insulated from the second end portion of the others of the first plurality of conductors.

Abstract: In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.

Abstract: An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.