Abstract: The present invention provides a clocking circuit for receiving a particular sized data word from a common input at a fixed frequency, writing the word to a number of individual memory cells in a storage device, reading another particular sized data word from the individual memory cells at a second particular frequency and presenting the data words to a common output at the second frequency. The storage device can be implemented as a memory array but is not limited to a memory array. The size of the words written to the storage device can be larger, smaller or the same as the size of the word read from the storage device. The present invention uses a multi-bit write counter to distribute a write timing signal at a particular frequency to a number of decoder and multiplexer blocks and a multi-bit read counter to distribute a read timing signal at a second particular frequency to a number of sense amplifier blocks.

Abstract: The present invention relates to a method of forming a dielectric film, a semiconductor device comprising the same, a method of operating a plasma enhanced chemical vapor deposition apparatus and a method of manufacturing a semiconductor device comprising the dielectric film.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: A block selecting scheme for a memory device. The block selecting scheme includes a sub word line driver circuit having multiple sub word line drivers and an inverter circuit. For one embodiment, the sub word line driver circuit includes four sub word line drivers. Each sub word line driver is used to select the sub word line for a corresponding memory block. Each of the sub word line drivers is coupled to a global word line via the inverter circuit. Furthermore, each of the sub word line drivers operates as an inverter. By coupling the global word line and each of the sub word lines via two inversion circuits, the global word line and the sub word lines are typically at the same voltage level. Thus, the deleterious effect of shorting between adjacent global word lines and sub word lines is substantially reduced. Furthermore, by grouping more than two sub word line drivers together, the overall die size of the memory device may be reduced.

Abstract: A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts.

Abstract: A pin-configurable frequency synthesizer for providing a choice of physical pin assignments/configurations without costly design and/or bonding changes. A functional block, having a plurality of functional conductors, is provided. The pin-configurable frequency synthesizer is housed in a chip package that includes a plurality of physical pins. A configuration matrix having a plurality of transmission circuits for connecting the functional conductors to the physical pins is also provided. A control circuit for controlling the transmission circuits of the configuration matrix is further provided. This control circuit includes programming logic and a logic array for generating control signals for each of the transmission circuits of the configuration matrix. These control signals direct the transmission circuits to selectively couple each functional conductor to a respective physical pin in accordance with a desired pin assignment.

Abstract: The present invention concerns data transition method and apparatus for driving a set of write data signals to an inactive (or deasserted) state upon completion of a WRITE to a particular group of memory cells. The present invention drives the write data signals to a an inactive state to end a WRITE without waiting for the end of the write control pulse. The present invention triggers a group of data write buffers to drive one of the write data signals to a "0" at the beginning of the WRITE control pulse or at a data input transition during a WRITE. A delayed transition of the write data signals may be used to drive both the write data signals to a "1"? to end the WRITE within a particular memory group. The write data transition detection is accomplished at the write data inputs of the groups of memory cells without relying on global chip data input pin transition detection and pulse width setting.

Abstract: An apparatus for protecting an integrated circuit against damage from electrostatic discharges (ESD) includes a single ESD bus that is connected to multiple input pads through a respective diode. The ESD bus is isolated from the positive power supply bus V.sub.DD. The ESD bus is coupled to the negative power supply bus V.sub.SS by a FET-triggered SCR circuit. ESD charge on an input pad forward biases the respective diode and charges the ESD bus. When the voltage of the ESD bus reaches a predetermined threshold voltage, the FET breaks down, and triggers the SCR circuit to shunt the charge on the ESD bus to V.sub.SS. The threshold voltage is selected such that, in normal operation, voltages higher than V.sub.DD may be applied to the input pad without input leakage current.

Abstract: The present invention concerns a method and apparatus that generally prevents an output glitch in a sense amplifier during a transition from a strong zero to a weak zero. When multiple cells are turned on, a virtual ground node is raised high due to the current flowing through the virtual ground device. A recover node is generally held close to the read product term line RPT. When a transition from a strong zero occurs, the recover node swings to VCC and provides conductance on the virtual ground node which generally eliminates the glitch.

Abstract: A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output signal. The control circuit includes a control transistor responsive to input control voltage V.sub.control. Connected between the source terminal of the control transistor and ground is a resistive element in parallel with an N-channel field effect transistor and a P-channel field effect transistor, each configured to operate in saturation. The resistor, and the N-channel, and P-channel transistors provide parallel current paths which, collectively, form a control current that corresponds to the frequency control signal. As the voltage control signal V.sub.control increases beyond a predetermined level, the transistors conduct, and carry a current that is proportional to the square of the input control voltage V.sub.control.

Abstract: The present invention provides a circuit for programming a logic device comprising a first register for shifting data to a memory array, a second register for decoding an address space for a particular word within the logic device. The memory array has an address input and a data input coupled to the first and second registers. One of the registers is implemented as a registered counter block while the other register can be implemented as either a shift register, for a low pin count design, and/or a parallel load register for a higher pin counter and higher performance design.

Abstract: A programmable hybrid fuse circuit having a laser fuse and an electrical fuse. The programmable hybrid fuse circuit includes a reference circuit, a current mirror and at programming circuit. The reference circuit generates a reference current mirror. The current mirror generates an output current in response to the reference current. The current mirror has at least one current output which is coupled to a programming circuit to receive the output current. The programming circuit includes a laser fuse and an electrical fuse coupled in a serial order such that either the laser fuse or the electrical fuse is capable of being blown during programming. The programming circuit generates an output signal having a first voltage level or a second voltage level dependent on whether one of the fuses is blown during programming.

Abstract: The present invention provides a pump circuit for generating a single variable high voltage output or multiple high voltage outputs that respond to one or more discrete inputs. The present invention utilizes a common pump circuitry to process the discrete voltage inputs. Each of the discrete voltage inputs can be a different input voltage and can be stepped up to a higher output voltage according to the design constraints of the pump circuitry. Since the pump circuitry is used for each of the inputs, the amount of chip real estate consumed is minimized to avoid redundancy. A switching system is implemented that detects which input has a voltage present and activates a particular path to the pump output accordingly.

Abstract: A clock recovery phase locked loop system is described. One embodiment has a voltage controlled oscillator divider (the signal of which is compared with a REFCLK divider signal), a voltage stimulus input where a test voltage is applied, a time stimulus input where a digital input with appropriate pulse width is applied and a monitor (output) where the results of the measurement can be observed. A test system is included which applies a series of analog voltages to the voltage stimulus input. For each analog voltage, the test system apply a series of pulses to the time stimulus input. By monitoring (a) the level on the monitor output and (b) the time at which it switches, the VCO gain can be calculated. This allows a direct measurement of VCO gain (K.sub.v) using conventional automatic test equipment used to test digital logic or memory devices.

Abstract: The invention relates to a transistor having a ramped gate oxide thickness, a semiconductor device containing the same and a method for making a transistor.

Abstract: An expansion bus is provided for use with bus systems of the type wherein only a single data signal or data packet may be transmitted over the bus at any one time, such as Ethernet bus systems. The expansion bus includes a set of repeater units each connected to a set of local transceivers respectively connected to remote bus masters, such as remote computers. The repeater units are interconnected by a single data bus. Collision detection and arbitration of usage of the single data line is achieved using a distributed symmetric arbitration system as follows. Each repeater unit has a dedicated activity line which is interconnected to each of the other repeater units. Each repeater unit also includes an identical arbitration unit connected to the respective activity lines. When a repeater unit receives data from a local transceiver for transmission onto the single data bus, the arbitration unit of the repeater unit asserts an activity signal onto the corresponding activity line.

Abstract: A configuration circuit includes a plurality of configuration cells where each configuration cell has (a) a nonvolatile pull-up cell coupled to an output node and for coupling to a first power supply voltage, and (b) a nonvolatile pull-down cell coupled to the nonvolatile pull-up cell and to the output node and for coupling to a second power supply voltage, where the nonvolatile pull-up cell includes a first nonvolatile transistor, and the nonvolatile pull-down cell includes a second nonvolatile transistor. The configuration cell may further include a volatile transistor in the nonvolatile pull-up and/or pull-down cells. In addition, the configuration cell may include a first erase device coupled to the first nonvolatile transistor for discharging charges on the floating gate of the first nonvolatile transistor and a second erase device coupled to the second nonvolatile transistor for discharging charges on the floating gate of the second nonvolatile transistor.

Abstract: The present invention concerns a method and apparatus that generally prevents a glitch from occurring in an output of a sense amplifier during a transition from a strong zero to a weak zero. The present invention detects the voltage difference between a virtual ground node and a read product term line and turns off a pull down of a first stage of the sense amplifier. The low on the read product term line generally causes a node between the first and second stage of the sense amplifier to swing high for both a strong or weak zero condition. A diode clamp generally limits the current drawn under the strong or weak zero condition by clamping the output of the first stage from going too high. When a transition from a strong zero to a weak zero occurs, the output of the first stage essentially remains high since the gate to source drive on the pulldown remains considerably weak.

Abstract: A power-on reset control circuit and associated method for deactivating a global power-on-reset signal based on whether circuitry, critical to correct functionality of an electronic system employing the power-on reset, is functioning correctly. The power-on reset control circuit comprises a control emulation circuit for transmitting a control signal through a first control line to indicate that the circuitry is operating correctly. The power-on reset control circuit further comprises a control verification circuit, coupled to the control emulation circuit through the first control line, for deactivating the global power-on reset signal upon receiving an active local power-on reset signal indicating that the power source is providing a voltage at an operating threshold level and the active control signal from the control emulation circuit.

Abstract: A reconfigurable buffer circuit capable of producing an active high or an active low output signal in accordance with a stored control parameter that is input to the buffer circuit. The reconfigurable buffer circuit has an output buffer that outputs a buffered output signal corresponding to an input signal. The reconfigurable buffer control circuit also has a control circuit that receives and stores an inputted control parameter, and receives at least one control signal from a control signal source. Based on the stored control parameter and the at least one control signal received from the control signal source, the control circuit produces the input signal.