Abstract: A method and apparatus for eliminating all unnecessary switching/toggling of bus signals is provided. A first circuit that is coupled to a first and second bus is provided. This first circuit selectively couples (i.e., transparently passes) a first signal from the first bus to the second bus in response to a control signal. A control/decoder circuit, coupled to the first circuit, generates the control signal based upon whether or not a bus cycle on the first bus is directed to a device coupled to the second bus. If the address is directed toward a device coupled to the second bus, the present invention transparently passes the bus signals on the first bus to the second bus. If not, the control/decoder circuit instructs the first circuit not to propagate the bus signals from the first bus to the second bus. In other words, the value of the bus signals on the second bus are unchanged.

Abstract: A method of forming a multi-layer suicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.

Abstract: A non-linear integrated phase locked loop circuit includes a phase detector for receiving a data signal and a clock pulse and for outputting a pump-up signal and a pump-down signal, a pulse divider connected to the phase detector for receiving the pump-up signal and the pump-down signal and producing a first output at predetermined multiples of the pump-up signal and a second output at predetermined multiples of the pump-down signal. A pulsed filter or integrator is connected to the pulse divider for receiving the first output and the second output and providing a frequency control signal for a voltage controlled oscillator. A three state amplifier is connected to the phase detector for receiving the pump-up signal and the pump-down signal and providing a phase control signal for a voltage controlled oscillator. The voltage controlled oscillator is connected to the pulsed filter and the amplifier for receiving the frequency control signal and the phase control signal and producing a corresponding output.

Abstract: A method for coding programming instructions in a complex programmable logic device (CPLD). In one embodiment, a CPLD has an instruction storage element comprising a first number of bits and requiring a first number of clock cycles to load the first number of bits. A novel method is used to instruct the device to perform at least one function comprising the steps of serially shifting a first instruction into the instruction storage element in a second number of clock cycles, and serially shifting a second instruction into the instruction storage element in a third number of clock cycles. The third number of clock cycles may be less than the first number of clock cycles. The third number of clock cycles may also be less than the second number of clock cycles. In one embodiment, the third number of clock cycles comprises one clock cycle.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: The present invention disables defective rows in a FIFO or other buffer where the word lines of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are substituted, as needed, for one or more defective rows. As a result, a defective row can be disabled without effecting the operation of the FIFO, particularly the read or write data path. In one example, the disabling effect is achieved by using one or more laser fuses. The present invention can be used to effectively bypass any single shift register element or a multiple number of shift register elements.

Abstract: A non-inverting pass gate local wordline scheme for block architecture memory arrays is described which includes two switches connected in parallel which may be driven by complementary control signals. A clamping switch may be connected to the local wordline to clamp the local wordline to a power supply voltage at a low logic level whenever the pass gate blocks an input signal. When a particle or defect creates a short which short circuits a local wordline to a global wordline, the global wordline may be permanently disabled by pulling it LOW. Regardless of the states and/or polarities of the BLOCK and BLOCK signals, the local wordline is permanently held LOW because the pass gate is non-inverting. The present invention may thus reduce power in a memory device by preventing a row of memory cells from unnecessarily drawing unused and/or unusable current.

Abstract: A state machine design which can be used to realize extremely short flag generation delays, also realizing the benefit of having an extremely high MTBF. A set of next state variables are generated from a combination of three previous state variables and three additional inputs representing a logical "OR" of a read half-full and write half-full flag WRH, an external write clock input, and an external read clock input. The next state variables are derived from a product of the previous state variables, a complement signal of the previous state variables, and the signal WRH. The half-full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal.

Abstract: A multi-port network interface device including a transmit data bus; a receive data bus; a medium access controller (MAC) and physical signaling (PLS) circuit, coupled to the transmit and receive data buses, and configured to interface to a network layer; at least one transmitter, coupled to the transmit data bus, and configured to transmit data to a physical layer; at least one receiver, coupled to the receive data bus, and configured to receive data from the physical layer; a local collision detector, coupled to the transmit and receive data buses, and configured to detect local collisions on the physical layer; a near end collision detector, coupled to the receive data bus, and configured to detect near end collisions on the physical layer; and a jabber detector, coupled to the transmit data bus, and configured to monitor a length of data transmissions.

Abstract: A power-on reset control circuit and associated method for deactivating a global power-on-reset signal based on whether circuitry, critical to correct functionality of an electronic system employing the power-on reset, is functioning correctly. The power-on reset control circuit comprises a control emulation circuit for transmitting a control signal through a first control line to indicate that the circuitry is operating correctly. The power-on reset control circuit further comprises a control verification circuit, coupled to the control emulation circuit through the first control line, for deactivating the global power-on reset signal upon receiving an active local power-on reset signal indicating that the power source is providing a voltage at an operating threshold level and the active control signal from the control emulation circuit.

Abstract: A programmable logic device includes a plurality of logic blocks coupled to an interconnect matrix, wherein one of the plurality of logic blocks comprises configurable memory logic having control logic coupled to a storage element. The control logic receives a plurality of control signals from the interconnect matrix and performs substantially all logic functions required for the configurable memory logic to selectively function as each of a plurality of memory devices. The plurality of memory devices includes a first-in-first-out (FIFO) memory device, a last-in-first-out (LIFO) memory device, a single-port memory device (e.g. single-port SRAM) and a multi-port memory device (e.g. dual-port RAM). Additionally, multiple logic blocks may comprise configurable memory logic. Each logic block may perform a different memory function. These logic blocks can be cascaded together to form memory devices with greater memory depths and/or widths than possible with a single logic block with configurable memory logic.

Abstract: A circuit for synthesizing, from a first signal having a first frequency, a second signal having a second frequency. This synthesis includes using a delay locked loop in combination with a minimal amount of logic circuitry to generate a synthesized output signal which is completely deterministic and does not require any analog control.

Abstract: A method for programming or testing a CPLD using an additional read register. In one embodiment, the method comprises: instructing the CPLD in one instruction to load program data, load address information and program the program data into a memory location having an address defined by the address information; loading the program data into a first data storage element and the address information into an address storage element; programming the program data into the memory location; instructing the CPLD to read verify data from the memory location; and capturing the verify data into a second data storage element. The second data storage element comprising a read registers. The novel method further comprises comparing the verify data with the program data. The verify data and the program data may be compared within the CPLD or the verify data may be output from the CPLD and compared with the program data externally.

Abstract: The present invention concerns an improved charge pump. The charge pump efficiently charges a voltage signal while reducing its power consumption. The charge pump includes at least one diode configured to receive a voltage signal. Coupled to the diode(s) is at least one capacitive device that is capable of coupling charge onto the diode(s). For one embodiment, the capacitive device provides a constant capacitance to more efficiently charge the voltage signal. The charge pump also includes an oscillating circuit that is capable of providing each capacitive device with an oscillating signal that alternates between a first voltage level and a second voltage level at a predetermined frequency. The oscillating circuit includes an odd number of N inverters coupled in a ring wherein an output of the Nth inverter is coupled to the input of the first inverter.

Abstract: A complex programmable logic device (CPLD) is disclosed which includes a set of logic blocks each containing a product term array and a set of macrocells. A clocking arrangement is provided which allows selection between synchronous and asynchronous clock signals for input to each macrocell. The clocking arrangement is hierarchical. More specifically, a synchronous clock multiplexer is provided, within each logic block, for reducing an input set of N synchronous clock signals, and their complements, to a reduced set of M synchronous clock signals. The selected synchronous clock signals, and J product term asynchronous clock signals, or their complements, provided by the corresponding product term array, are routed into each of the macrocells of the logic block. An additional multiplexer is provided within each macrocell for selecting one clock signal from among the M synchronous clock signals and the J product term signals.

Abstract: A bidirectional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2. If the voltage on one of the nodes, IO1 or IO2, rises with a fast input edge rate, tending to cause the gate voltage V1 to go too high due to capacitive coupling (source-gate or drain-gate), node N1 is coupled through an appropriate capacitor, C1 or C2, to another node N3, which is normally held low by a transistor MN9. The voltage on N3 drives the gate of a transistor MN10, connected to node N1, to pull the gate voltage V1 of MN1 low, tending to discharge the capacitive coupling due to the overlap capacitance of MN1, which tends to turn MN1 OFF and also allows the voltage V1 to decay very quickly, so as to prevent some of the charge from IO1 getting through to IO2.

Abstract: The present invention concerns a delay circuit that provides a fixed amount of delay that is generally independent of process variations. An input resistance is provided that may be presented to a threshold device, such as an inverter, that may then be presented as an output. The output of the threshold device may also be presented through a feedback path comprising a capacitive device to the input of the threshold device. The feedback through the capacitive load actively resists the movement of the load. As a result, the delay provided by the circuit is generally resistant to process variations.

Abstract: The present invention concerns a circuit and method for disabling the load transistors from the bitlines of a memory array without requiring a fuse. After a particular column is disabled in a redundant memory array system, a short between the particular bitline and ground is detected by a control circuit that shuts off the appropriate bitline load. The disconnecting of the particular bitline load does not affect any of the normal read or write operations of the circuit. The present invention detects whether the short exists and provides the disabling feature while maintaining the ability to distinguish between a normal write condition and a condition that resembles a bitline short. After a write occurs, the bitline load will remain active. The ability of the present invention to distinguish between a normal write and a bitline short allows for transparent operation.

Abstract: An asynchronous anticontention circuit for a bi-directional bus. The asynchronous anticontention circuit comprises an anticontention circuit coupled to an asynchronous delay circuit. The anticontention circuit receives a driver select signal and generates a first signal and a second signal. The first signal and the second signal each have an active state and an inactive state. When the driver select signal is in a first logic state, the first signal is in the inactive state and the second signal is in the active state. When the driver select signal transitions from the first logic state to a second logic state, the anticontention circuit transitions the second signal from the active state to the inactive state. The asynchronous delay circuit couples the transition of the second signal to the anticontention circuit after a delay of time. After the delay of time, the anticontention circuit transitions the first signal from the inactive state to the active state.

Abstract: The present invention provides power saving features that can be used in a computer or other device employing an internal clock to dynamically change the frequency at which the clock operates to respond to demands upon system resources. For example, the CPU clock in the synchronous logic core may be changed dynamically to reduce power consumption without causing a CPU lock-up. A PLL clock internal to the CPU has a reduced sensitivity to external clock changes. The present invention provides a means to incrementally change the internal clock frequency by intermittently stopping the output of the internal clock.