Abstract: An electrically-erasable programmable read-only memory (EEPROM) cell includes a split-gate read transistor and a buried N-plate control gate. The split gate transistor includes a drain and source regions formed in a P-type silicon substrate with a channel formed therebetween. Silicon dioxide is disposed over the drain, channel and source regions wherein the oxide overlying the drain and a portion of the channel is thicker compared to the thickness of the oxide overlying the remainder of the channel and the source. A layer of polycrystalline silicon is disposed over the channel. The buried N-plate control gate is spaced laterally from the source, drain, and channel regions. The floating gate overlying the channel extends also over the buried N-plate control gate. The split gate structure effectively realizes a pair of in-series gates, each having a different threshold voltage in accordance with the thickness of the oxide used.

Abstract: The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.

Abstract: A circuit provides a duty cycle adjustment through a gate delay for operation at various output voltage levels. The delay may be provided through an OR gate and an AND gate that will generally modulate the duty cycle received at the input since most of the strength of the predriver resides in the pullup and pulldown transistors. The circuit may operate at a number of output voltage levels, including, but not limited to, CMOS and TTL levels. The implementation of the circuit also provides the advantage of parasitic load matching that may reduce EMI.

Abstract: A method and apparatus to eliminate the problem of requiring sizing of the row and column decoders according to the pitch of the cells in the memory array is to decouple the decoder cell pitch from the memory cell pitch without causing the chip area to increase dramatically. Decoupling is accomplished by driving the array from both sides for row drivers and by driving the array from both the top and bottom for column drivers. This is achieved in one embodiment by driving alternating rows from opposite sides for row decoders. Even numbered rows are driven from one side and odd numbered rows are driven from the other side. Alternating columns are driven from both the top and bottom. For example, odd numbered columns are driven from the top while even numbered columns are driven from the bottom. In a second embodiment, predetermined rows are driven from one side while the others are driven from the other side.

Abstract: An improved burst address generator that is coupled to a memory array receives as its inputs a N-bit start address and dynamically generates a burst sequence of 2.sup.N decoded addresses. The burst address generator is responsive to a mode-select signal that determines whether the burst address generator operates in a linear mode or a non-linear mode. A decoder is provided for decoding the start address. A wrap-around up-down 2.sup.N -bit shift register, coupled to the address decoder, receives the decoded start address from the address decoder and dynamically provides the proper burst address sequences in accordance to the selected mode. A start address storage element is also coupled to the shift register and the address decoder to keep track of the start address.

Abstract: A method and apparatus for serially programming or testing a programmable logic device. In one embodiment, the method comprises the steps of: instructing the programmable logic device, in one instruction, to load program data, load address information and program the program data into a memory location defined by the address information; loading the program data into a data storage element and the address information into an address storage element; and programming the program data into the memory location. The novel method further comprises the step of instructing the programmable logic device, in one instruction, to read verify data from the memory location, to compare the verify data with the program data and to program the program data into the memory location. The novel method further comprises the steps of comparing the verify data with the program data and generating a verify signal.

Abstract: A method and circuit for hiding a refresh of DRAM cells in a memory device. One embodiment of the circuit includes a selection circuit configured to select a first row of DRAM cells in the memory circuit in response to an active control signal. As a result, data may be read from or written to at least one of the DRAM cells in the first row. The selection circuit is also configured to couple a refresh address to a second row of DRAM cells in the memory circuit in response to an inactive state control signal. The second row of cells is refreshed when the selection circuit accesses the second row. For one embodiment, the DRAM cells are four transistor DRAM cells.

Abstract: A method of encapsulating a dielectric. According to the method of the present invention, a disposable post is formed over a portion of a substrate. Next, a first dielectric layer is formed over the substrate and the disposable post. A second dielectric layer is then formed over the first dielectric layer. Next, a third dielectric layer is formed over the second dielectric layer. A portion of the third dielectric layer is then removed so as to reveal the disposable post. The disposable post is then removed to form an opening.

Abstract: A damascene method of forming planarized interconnects between conductive material layers in trench-isolated cells in an integrated circuit is disclosed. The method includes depositing and patterning a photoresist layer over a portion of an integrated circuit with isolated devices to expose a portion of an isolation trench separating the conductive layers of isolated devices desired to be interconnected. The method further involves etching a portion of the trench refill material, removing the photoresist layer, and depositing a second conductive layer in the trench to replace the material removed by the etching step.

Abstract: The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable.

Abstract: An ultra-low power pumped n-channel transistor output buffer with self-bootstrapping includes an n-channel pullup transistor as the primary pullup device. A gate-to-source capacitance C.sub.gs of the pullup transistor is used to self-bootstrap the input data signal. A pass n-channel transistor is connected between the input data signal, and the gate of the pullup transistor, and is biased on a gate terminal thereof by a charge pump having a voltage magnitude one device threshold higher than the device operating rail V.sub.cc. The pass transistor, so biased, permits the input data signal, which may have a magnitude of V.sub.cc, to charge C.sub.gs. An over-voltage can be developed on the gate of the pullup transistor by the self-bootstrapping effect of C.sub.gs. The pass transistor, in addition, so biased, prevents such over-voltage on the pullup transistors gate from being shorted to V.sub.cc through a driving device.

Abstract: The present invention concerns a method and apparatus for disabling columns using a local fuse decoding system. The present invention uses local decoding in order to use a number of fuses that is less than the number of columns in order to disable column failures. This is particularly useful when the fuse pitch is greater than the column pitch which does not allow for a fuse to be implemented in each column.

Abstract: The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier blocks. Each of the sense amplifier blocks receives both a data input signal from the memory array and the timing signal at all times. When a particular timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from the corresponding memory array and is presented to the output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to read multiple width words from the memory array.

Abstract: A method and apparatus for sensing the state of a memory cell and equalizing bit line voltages without using ATD circuitry. One embodiment of the present invention is a memory device that includes a memory cell coupled to a pair of bit lines, a bit line load circuit coupled to the bit lines, an equalization circuit coupled to the bit lines, and a sense amplifier circuit having inputs coupled to the bit lines and an output coupled to the equalization circuit. The memory cell may be an SRAM cell with a pair of cross-coupled inverters. The equalization circuit may be an SRAM cell with a pair of inverters that are not cross coupled. The inputs of the inverters in the equalization circuit may receive signals output by the sense amplifier circuit, and the outputs of the inverters may be coupled to the pair of bit lines. The sense amplifier senses data output by the memory cell to the bit lines, and generates output signals.

Abstract: An apparatus for protecting an integrated circuit against damage from electrostatic discharge (ESD) includes an ESD bus that is connected to multiple input pads through a respective diode. The ESD bus--the node to be protected--is coupled to the negative power supply bus (V.sub.ss) by a FET-triggered SCR circuit. In particular, the SCR circuit includes, equivalently, a PNP bipolar transistor, and an NPN bipolar transistor interconnected so that each transistor receives base current from the collector terminal of the other. A field effect transistor (FET) is configured to trigger the SCR into conduction, to thereby provide a low-impedance path to safely shunt ESD charge. The drain terminal of the FET is connected to an intermediate node of a resistance between the ESD bus, and the PNP emitter terminal. ESD charge on an input pad of the integrated circuit forward biases the respective diodes, and charges the ESD bus.

Abstract: In a memory device, a write operation only to a desired memory location may be performed by recognizing an address transition and preventing a memory write to an undesired memory location in response thereto. The memory write to the undesired memory location may be prevented by blocking the memory write using an address transition detection (ATD) signal. This may include decoupling a bitline (e.g., using a passgate transistor) from a data signal in response to the ATD signal. Alternatively, the memory write may be prevented by pulsing an ATD signal to delay the memory write to the undesired memory location and then deasserting a data write signal to block the memory write. In one embodiment, a circuit which includes a memory cell and an isolation circuit coupled to the memory cell is provided. The isolation circuit may be configured to prevent a memory write to the memory cell in response to an ATD signal.

Abstract: A method for varying the type of function selected on a chip (for example, after completion of manufacturing) may include the steps of providing predetermined fuse arrangements which individually or in combination correspond to each type of function on the chip and providing disable control lines having fuses to each of the predetermined fuse arrangements. When one of the types of circuits is selected, the predetermined fuse arrangement individually or in combination corresponding to that selected type of function is blown. The blowing of fuses may change the functionality of the chip directly or may perform a complex procedure such as controlling a portion of a decoding scheme which may radically change the function of the chip. To prevent further blowing of predetermined fuse arrangements, the fuses in disable control lines to each of the predetermined fuse arrangements may be blown, eliminating further selection of types of function.

Abstract: The present invention provides a clocking circuit allowing individual macrocells in a particular macrocell block of a CPLD to use different polarities of the same clock. The input clock pin can now drive all the macrocells directly, which can eliminate additional buffering states and improve the clock to out timing, Tco, by (for example) 300 ps. The clocks are presented directly to the clock selection multiplexers for each macrocell. Additional functioning may be realized by implementing additional configuration bits inside the clocking architecture.

Abstract: A clock synthesizer is disclosed that includes a phase-locked loop circuit having two modes of operation: a non-slewing mode of operation, and a frequency-slewing mode of operation. During the power-up of the system, the PLL is controlled to operate in the non-slewing mode of operation to effect rapid variations in the output frequency. A power-on reset circuit is disclosed which determines when the system is in the power-up interval, and generates a power-on-reset signal to so indicate. The PLL operates in a frequency-slewing mode after power-up to provide controlled transitions in the frequency of the output reference signal of the PLL. A phase-locked loop circuit having structure to implement both modes is provided, as well as an adjustable lock detector circuit. The output of the lock detector, a logical lock signal, is used to enable the frequency-slewing mode of the PLL circuit.

Abstract: A level shifting circuit includes first and second load, gain and reference transistors. The first and second load transistors each have a source-drain path arranged between Vdd and Vss power supply voltages, and a gate coupled to the Vss power supply voltage. The first and second gain transistors each have a source-drain path arranged between the respective source-drain paths of the first and second load transistors and the Vss power supply voltage, and gates serving as respective differential input nodes. The first and second reference transistors each have a source-drain path arranged between the Vdd and Vss power supply voltages, and a gate coupled to respective first and second nodes serving as respective differential output nodes, the first node connecting the source-drain path of the first load transistor with the source-drain path of the first gain transistor, and the second node connecting the source-drain path of the second load transistor with the source-drain path of the second gain transistor.