Abstract: A method and apparatus for recovering timing information from a ternary signal includes transforming a ternary signal into a binary signal while retaining the necessary timing information. A two facet circuit initially receives a ternary signal, one that includes three levels of values. A first facet of this circuit transforms the ternary signal into two binary signals, each having one of the three levels represented by one value and both having the same level represented by the other value. The second facet of this circuit combines the two binary signals to produce a third binary signal that has one value representing one level and another value representing the two other levels.

Abstract: An output buffer circuit of a semiconductor memory device can produce multiple output buffer drive strengths. An electronic system including a memory device in which such an output buffer circuit is implemented can include a mechanism for enabling the output buffer drive strength to be easily selected by a user of the memory device (such as an assembler of an electronic system including the memory device) from the multiple possible drive strengths. The invention thus enables a memory device to be easily configured to have an output buffer drive strength that is compatible with a wide variety of electrical loads to be driven by the output buffers of the memory device.

Abstract: A lock detector suitable for detecting when an output signal of a phase-locked loop circuit is phase-locked to an input reference signal. The lock detector includes a pair of delay lines, that are adjustable, which are used to create a window signal around the reference clock signal. UP and DOWN signals from the PLL circuit are fed to an OR gate to generate an actual out-of-lock signal. When the PLL circuit is phase-locked within an acceptable phase error range, the UP, and DOWN signals, if any, will appear within the generated window signal. When the PLL circuit is not phase-locked within the acceptable phase error range, the UP, and DOWN signals occur outside of the window. The window signal, and the output of the OR gate are connected to an AND gate to generate a gated out-of-lock signal. The gated out-of-lock signal is connected to a switched-capacitor charge pump.

Abstract: The present invention describes a method for testing an electronic part which may be an integrated circuit by using an air brush spray gun to apply an atomized flux coating to the part. The purpose of the method is to simulate soldering and is used on only a sample of parts as part of a reliability procedure before subjecting the part to an additional stress test or before actually soldering the part. The method comprises the steps of: spraying each part with an atomized flux coating; heating each part to simulate a soldering process; and removing each part from a heat source.

Abstract: Circuit for preventing the improper functioning of a CMOS output buffer that may occur due to the fact that since the output buffer P-channel may be coupled between a supply voltage and an output pad. If the pad is driven higher than the supply voltage by an external source, current may be injected into the parasitic diodes of the source/drain of the transistor.

Abstract: A method is described that writes a first and a second data of a first data width into a memory that stores data at a second data width greater than the first data width. The method includes the step of selecting via a select circuit a plurality of memory cells that correspond to the second data width from a memory array of the memory. The first data is then written into a first number of the memory cells corresponding to the first data width while writing invalid data into a second number of the memory cells also corresponding to the first data width during a first write operation. The second data is then written into the second number of the memory cells while again writing the first data into the first number of the memory cells during a second write operation. A memory that can operate with either the first data width or the second data width without changing its column select circuit is also described.

Abstract: A state machine for generating a flag that represents the fullness of a FIFO buffer is disclosed. The present invention generates a set of next state variables that are derived generally from a combination of three previous state variables and three additional inputs representing an internally generated look-ahead flag, an external write clock and an external read clock. The next state variables are derived specifically from a product of the previous state variables and complement signals of the previous state variables. The full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal and a look-ahead decoded internal full flag signal. An empty flag can be generated by switching the read and write clock inputs and changing the look-ahead decoded internal full flag to a look-ahead decoded internal empty flag.

Abstract: The present invention provides a circuit for distributing data from a common input source to a number of individual memory cells in a memory array. A multi-bit counter is used to distribute a timing signal to a number of decoder blocks. Each of the decoder blocks receives both a data input signal and the timing signal at all times. When a particular timing signal is present at a given decoder, the input signal containing a fixed width data word is passed through to the corresponding memory array for storing the data word. The present invention reduces the number of internal signal lines necessary to implement the control function and significantly reduces the chip area needed to generate the signal lines.

Abstract: A cache controller includes a hit determination circuit that is adapted to handle a non-symmetric cache. This hit determination circuit includes symmetric match circuit having a first input port for receiving addresses from a host processor bus and a second input port for receiving a tag entry from a cache tag memory. The symmetric match circuit compares the address to the tag entry and generates a symmetric match signal when there is a match between the address and the tag entry. A non-symmetric circuit that includes a first input port for receiving an address from the host processor bus and a second input port for receiving a predetermined pattern of bits is also provided. The non-symmetric match circuit generates a non-symmetric match signal when the address matches the predetermined pattern. A hit signal generator that is coupled to the symmetric match circuit and a non-symmetric match circuit generates a hit signal which indicates whether or not the current address is stored in the cache memory.

Abstract: A disposable post process allows openings to be created in a layer formed over a semiconductor wafer, for example to create self-aligned contacts. A layer of material is formed over a semiconductor wafer and subsequently patterned into posts which define the location and shape of openings to be formed in a subsequently formed planar layer. After the planar layer is formed to surround the posts, the posts are removed to create openings in the planar layer. These openings may then be used to form suitable contacts.

Abstract: The present invention provides a device for terminating a data bus. The present invention provides the proper termination without the use of external discrete components. The device can be programmed, at the chip level, to produce particular termination resistances that are commonly used. The present invention termination device uses a minimum of power dissipation which may be useful in applications that require minimum power consumption.

Abstract: The present invention concerns a circuit for implementing a low noise bias circuit that operates at 3 volts, 5 volts or any desired power supply voltage while avoiding production reconfiguration or post-production configuration. The present invention is implemented by using a current source designed to provide a constant current under differing conditions (e.g., such as a variation in temperature, a variation in power supply, or conditions encountered in a fast transistor process). The present circuit provides a means to adapt to varying conditions. The present circuit generally provides two bias signals that are typically used in a pre-driver circuit implementing NMOS and PMOS transistors.

Abstract: An OR array including a first multiplicity of OR devices, to which a second multiplicity of product term signals are variably distributed. Some product term signals are distributed to four OR devices, other product term signals are distributed two or three OR devices, and still other product term signals are distributed to only one OR device.

Abstract: An improved input ESD protection structure is disclosed that is suitable for use on high-voltage input pins, such as programming pins, of programmable integrated circuits such as programmable logic devices (PODs) programmable read-only memories (PROMs), or field programmable gate arrays (FPGAs). The input ESD protection structure includes a primary ESD protection FET for shunting ESD current from the input pad, and a secondary ESD protection FET, in combination with a series resistor, to limit the voltage appearing across the gate oxides of the input buffer. The primary protection FET is laid out in a multi-finger architecture wherein the drain n.sup.+ -type conductivity regions are overlapped with a depletion implant. The depletion implant extends from these drain regions, respectively, through channel regions toward the source regions.

Abstract: A method of forming an antifuse device. According to the preferred method of the present invention, a first metal layer comprising a first bulk conductive layer and the top capping layer is formed. Next, the capping layer is etched into a first patterned capping layer. An antifuse layer is then formed over the patterned capping layer and over the first bulk conductive layer. Next, a second metal layer comprising a bottom barrier layer and a second bulk conductive layer is formed on the antifuse layer. The second metal layer and the antifuse layer are then etched to form a metal post on the capping layer. The first bulk conductive layer is then etched in alignment with the patterned capping layer to form a first metal interconnect.

Abstract: A method of limiting or translating the voltages of input signals, and of generating output signals such that the input's high state and low state differ by a different voltage than the output's high and low state. The present invention also teaches a system comprising a level translator circuit having level translators controlled by an operational amplifier or by a Zener diode that regulates the voltage level on one side of the translators, the other side of the translators being regulated by an external power supply. The operational amplifier or Zener diode, in some embodiments of the present invention, ensures that the second side of the level translators are limited to a given reference voltage. Often, a resistor is connected to the Zener diode or to the output of the operational amplifier, and in some embodiments a resistor-capacitor network removes higher-frequency components from the voltage supply.

Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.

Abstract: A dummy cell in a memory array. The memory array includes a storage element for storing one of a first and a second state. The storage element is coupled to circuitry for reading the first or second state from the storage element. The storage element draws a first current when the first state is read by the circuitry. The storage element and circuitry are further coupled to the dummy cell which provides a reference voltage when the circuitry reads the first or second state from the storage element. The dummy cell draws a second current when the circuitry reads the first or second state from the storage element. The second current is not equivalent to the first the first current. In one embodiment, the dummy cell draws approximately half the current that the storage element draws when the circuitry reads the first state from the storage element.

Abstract: A lithographic patterning process uses multiple exposures to provide for relatively reduced pitch for features of a single patterned layer. A first imaging layer is exposed to radiation in accordance with a first pattern and developed. The resulting patterned layer is stabilized. A second imaging layer is subsequently formed to surround the first patterned layer, exposed to radiation in accordance with a second pattern, and developed to form a second patterned layer. As the first patterned layer has been stabilized, the first patterned layer remains with the second patterned layer to produce a single patterned layer. For another embodiment, a single imaging layer is patterned by exposure to radiation in accordance with two separate patterns. An exposed portion of the imaging layer is suitably stabilized to withstand subsequent lithographic process steps.

Abstract: A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.