Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for detecting the drift of the data valid window in a transaction. An embodiment operates by configuring a data capture range comprising data capture points, measuring values of a signal at the data capture points, and detecting the drift of the data valid window based on the values at the data capture points.

Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.

Abstract: A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation.

Abstract: A method for detecting a finger at a fingerprint sensor includes detecting a presence of an object at a fingerprint sensor and, in response to detecting the presence of the object, acquiring image data for the object based on signals from the fingerprint sensor. The method further includes, for each subset of one or more subsets of the image data, calculating a magnitude value for a spatial frequency of the subset, and identifying the object as a finger based on comparing the magnitude value to a threshold.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.

Abstract: Systems, methods, and devices enable the implementation of antenna diversity techniques. Devices include a first wireless communications device that includes a plurality of antennas, and a transceiver coupled to the plurality of antennas and configured to send and receive data in accordance with a wireless transmission protocol, while the peer wireless communication device may have a single antenna or multiple antennas. Devices also include a processor configured to, in a first mode, calculate an angle of arrival (AoA) with the plurality of antennas or an angle of departure (AoD) associated with single antenna, and, in a second mode, send data to and receive data from a second wireless communications device via at least a first antenna of the plurality of antennas, where the first antenna is selected by the processor based on one of a first plurality of signal measurements between the first and second wireless communications devices.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.

Abstract: An electronic device includes a first electronic circuitry portion configured to connect a VCONN supply terminal of a Universal Serial Bus Type-C (USB-C) controller to a first configuration channel (CC) terminal of a plurality of CC terminals of the USB-C controller. The first CC terminal of the USB-C controller is to be directly connected to a first CC terminal of a plurality of CC terminals of a USB-C receptacle. The electronic device further includes a second electronic circuitry portion electrically coupled to the first electronic circuitry portion and configured to detect a voltage across the first CC terminal of the USB-C controller and the VCONN supply terminal. The second electronic circuitry portion is to decouple the VCONN supply terminal from the first CC terminal of the USB-C controller when the voltage is greater than a predetermined threshold.

Abstract: An example electronic device includes a first switch and a second switch that are each coupled to an overvoltage detection and protection circuit. The first switch is configured to connect a first sideband use (SBU) terminal of a Universal Serial Bus Type-C (USB-C) controller to a SBU crossbar switch of the USB-C controller. The second switch is configured to connect a second SBU terminal of the USB-C controller to the SBU crossbar switch. The overvoltage detection and protection circuit is configured to deactivate the first switch or the second switch when a voltage exceeding a predetermined threshold is detected on a terminal of the first switch or the second switch.

Abstract: An electronic device includes a first switch configured to connect a VCONN supply terminal of a Universal Serial Bus Type-C (USB-C) controller to a first configuration channel (CC) terminal of the USB-C controller in response to a USB-C connector being in a first orientation. A first current may flow through the first switch. The electronic device also includes an overcurrent component coupled to the first switch. The overcurrent component includes a second switch associated with the first switch. The second switch has a second current associated with the first current. The overcurrent component is configured to determine whether the first current is greater than a threshold current based on the first current and the second current. The overcurrent component is also configured to close the first switch in response to determining that the first current is greater than the threshold current.

Abstract: An sense unit for inductive sensing or capacitive sensing is described. The sense unit may include a first terminal coupled to a first node, a first electrode coupled to the first node, and a second terminal. The sense unit may include a second electrode coupled to the second terminal. In a first mode, a first signal is received at the first terminal and a second signal is output on the second terminal, where the second signal may be representative of a capacitance of the sense unit. The sense unit may include an inductive coil. The sense unit may include a first capacitor. The inductive coil and the first capacitor are coupled in parallel between the first node and ground. In a second mode, a third signal is received at the first terminal and a fourth signal is output on the second terminal.

Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

Abstract: Calibrating a Gaussian frequency-shift keying modulation index includes generating a training sequence of bits, shaping a pulse from the training sequence according to an initial modulation index, and converting the shaped signal to a transmission signal. The transmission signal is then either looped through a radio frequency core or processed by frequency deviation estimation hardware to determine a frequency deviation. The frequency deviation is converted to a new modulation index, and potentially a ratio between a target modulation index and a measured modulation index as a scaling factor. The process is then iteratively repeated until a threshold frequency deviation is achieved.

Abstract: An apparatus including a first signal generator of a force sensing circuit to output a first excitation (TX) signal on a first terminal and a second TX signal on a second terminal. The first terminal and the second terminal are configured to couple to a first force sensor and a reference sensor. The apparatus includes a first receiver channel coupled to a third terminal and a fourth terminal. The third terminal is configured to couple to the first force sensor and the fourth terminal is configured to couple to the reference sensor. The force sensing circuit is configured to measure a first receive (RX) signal from the first force sensor via the third terminal and a second RX signal from the reference sensor via the fourth terminal. The force sensing circuit is configured to measure a force value indicative of a force applied to the first force sensor.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: Systems, apparatus, and methods measure a signal provided by a capacitance sensor, the signal indicative of a presence of an object proximate to the capacitance sensor. Responsive to measuring the signal, embodiments access control information in a memory to determine whether the signal is associated with a first qualifying event of the control information. Responsive to determining that the signal is associated with the first qualifying event, embodiments control a power consumption of a communication device.

Abstract: A sense unit for inductive sensing or capacitive sensing is described. The sense unit may include a first terminal coupled to a first node, a first electrode coupled to the first node, and a second terminal. The sense unit may include a second electrode coupled to the second terminal. In a first mode, a first signal is received at the first terminal and a second signal is output on the second terminal, where the second signal may be representative of a capacitance of the sense unit. The sense unit may include an inductive coil. The sense unit may include a first capacitor. The inductive coil and the first capacitor are coupled in parallel between the first node and ground. In a second mode, a third signal is received at the first terminal and a fourth signal is output on the second terminal.

Abstract: Systems, methods, and apparatus receive a signal from a first wireless device through a first antenna, of a plurality of antennas, the signal including a first segment and a second segment. Responsive to detecting a change in the signal from the first segment to the second segment, embodiments traverse the plurality of antennas to receive the second segment through each of the plurality of antennas. Embodiments determine a plurality of phase samples, each associated with the second segment received through one of the plurality of antennas. Embodiment then use the plurality of phase samples to calculate direction data associated with the first wireless device.

Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.