Abstract: A spatial frequency based capacitive motion sensor and method of operating the same are disclosed. In one embodiment, the motion sensor includes an array of sense cells to capacitively sense capacitance variations induced by a surface in proximity to the array. The motion sensor further includes processing circuitry including a multiplexer and a processor to process motion dependent output signals from the array to measure motion of the surface in a direction parallel to a surface of the array. Generally, processor is adapted to execute a program to control the multiplexer to interconnect the sense cells of the array to configure the array as a comb-filter to detect at least one spatial frequency component of the capacitance variations, and to measure motion of the surface in a direction parallel to the array. Other embodiments are also disclosed.

Abstract: An sense unit for inductive sensing or capacitive sensing is described. The sense unit may include a first terminal coupled to a first node, a first electrode coupled to the first node, and a second terminal. The sense unit may include a second electrode coupled to the second terminal. In a first mode, a first signal is received at the first terminal and a second signal is output on the second terminal, where the second signal may be representative of a capacitance of the sense unit. The sense unit may include an inductive coil. The sense unit may include a first capacitor. The inductive coil and the first capacitor are coupled in parallel between the first node and ground. In a second mode, a third signal is received at the first terminal and a fourth signal is output on the second terminal.

Abstract: An apparatus includes a first antenna and a second antenna. A solid dielectric material is disposed between the first antenna and the second antenna. The solid dielectric material may alter radio-frequency signals received by the first antenna or the second antenna by reducing the propagation speed of the radio-frequency signals. This allows the angle of arrival of the radio-frequency signals to be determined.

Abstract: A memory device can include a memory cell array and a remap data structure. A remap data structure can include a mapping history section configured to store sets of mappings between logical addresses and the physical addresses of the regions, and a status section configured to identify one of the sets of mappings as a live set for the device. Control logic can be coupled to the memory cell array and the remap data structure and configured to enable access to the storage locations and remap data structure. Firmware update systems and methods, including firmware-over-the-air (FOTA), that include a memory device are also disclosed.

Abstract: A capacitance sensing device includes a transmit (TX) generator for generating a sequence of receive (RX) signals by applying each TX signal pattern in a sequence of TX signal patterns to a set of sensor electrodes. For each TX signal pattern in the sequence of TX signal patterns, and for each subset of three or more contiguous sensor electrodes of the set of sensor electrodes, the TX generator applies to the subset one of a first excitation signal and a second excitation signal. The plurality of subsets includes at least half of the sensor electrodes in the set of sensor electrodes. The capacitance sensing device also includes a sequencer circuit coupled with the TX generator. For each TX signal pattern in the sequence of TX signal patterns, the sequencer circuit determines a next subsequent TX signal pattern in the sequence based on a circular rotation of the TX signal pattern. The capacitance sensing device also includes a processing block coupled with the TX generator.

Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.

Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.

Abstract: An electronic device includes a power switch configured to receive a voltage on a first terminal. The first terminal is coupled to a voltage regulator. The power switch is also configured to provide the voltage to a second terminal. The second terminal is coupled to a VBUS terminal of a Universal Serial Bus Type-C (USB-C) connector. The electronic device also includes a protection circuit comprising a comparison component coupled to the first terminal and the second terminal. The comparison component is configured to detect a first voltage at the first terminal detect a second voltage at the second terminal. The protection circuit is configured to determine whether the second voltage is within a threshold voltage of the first voltage and adjust operation of the power switch in response to determining that the second voltage is within the threshold voltage of the first voltage.

Abstract: Systems, methods, and devices enable coexistence of traffic for collocated transceivers. Methods may include generating, using a processing device, a target-wake-time (TWT) agreement, the TWT agreement being determined based on availability of a first transceiver and a plurality of wireless devices. The methods may also include generating, using the processing device, a medium access schedule for the first transceiver based on a transmission parameter of a second transceiver, the second transceiver being collocated with the first transceiver and sharing a transmission medium with the first transceiver, and the medium access schedule being a TWT schedule. The methods may further include transmitting the TWT schedule to the plurality of wireless devices, the TWT schedule identifying a plurality of wake times and a plurality of sleep times to the plurality of wireless devices.

Abstract: Techniques for multi-phase self-capacitance (MPSC) scanning of a sensor array are described herein. In an example embodiment, a device comprises a sensor logic coupled to a processing logic. The sensor logic is configured to concurrently sense multiple sensor elements of the sensor array in each of multiple scanning operations in order to obtain multiple measurements, where each measurement represents a collective charge of the multiple sensor elements accumulated during a corresponding scanning operation. The processing logic is configured to determine data values based on the obtained multiple measurements, where the data values respectively represent self-capacitances of the multiple sensor elements.

Abstract: Semiconductor devices including non-volatile memory devices and methods of fabricating the same are provided. Generally, the memory device includes a gate structure, a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. In one embodiment, the multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide, and the first and the second dielectric layers include a nitride. Other embodiments are also disclosed.

Abstract: A method includes receiving at a wireless access point a first probe request from a first client device requesting connection with the wireless access point via a first frequency band, queueing the first client device in response to an indication that the first client device supports connection via the second frequency band, and in response to receiving at the wireless access point a second probe request from the first client device requesting connection with the wireless access point via the second frequency band, establishing a connection between the wireless access point and the first client device using the second frequency band.

Abstract: Techniques for optical monitoring of corrosion are described herein. In an example embodiment, an optical monitor includes a target disposed within the optical monitor and exposed to ambient air, where exposure to the ambient air produces a change in an optical property of the target. The optical monitor also includes a light emitter to illuminate the target and an optical detector to generate a signal based on light reflected from the target. A processing device disposed within the optical monitor is configured to activate the light emitter and to receive and process the signal from the optical detector.

Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.

Abstract: Apparatuses and methods of distinguishing between a finger and stylus proximate to a touch surface are described. One apparatus includes a first circuit to obtain capacitance measurements of sense elements when a conductive object is proximate to a touch surface. The apparatus also includes a second circuit coupled to the first circuit. The second circuit is operable to detect whether the conductive object activates the first sense element, second sense element, or both, in view of the capacitance measurements. To distinguish between a stylus and a finger as the conductive object, the second circuit determines the conductive object as being the stylus when the second sense element is activated and the first sense element is not activated and determines the conductive object as being the finger when the first sense element and the second sense element are activated.

Abstract: An example system drives one or more transmit signals on first electrodes disposed in a first layer and propagating electrodes disposed in a second layer. The system measures a capacitance of sensors through a of second electrodes. Each second electrode crosses each first electrode to provide a plurality of discrete sensor areas, each discrete sensor area associated with a difference crossing and including a portion of at least one propagating electrode. Each second electrode is galvanically isolated from the first electrodes and the propagating electrodes.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.

Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.

Abstract: Disclosed herein is an apparatus that includes a ferroelectric capacitor disposed on a damascene barrier film, and fabrication methods thereof. The damascene barrier film includes a hydrogen barrier region and an oxygen barrier region, with the oxygen barrier being in contact with a bottom surface of the ferroelectric capacitor. Other embodiments are also disclosed herein.