Patents Assigned to Cypress Semiconductor
  • PROGRAMMABLE INPUT/OUTPUT CIRCUIT
    Publication number: 20190214990
    Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.
    Type: Application
    Filed: November 16, 2018
    Publication date: July 11, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
  • METHOD FOR PROVIDING READ DATA FLOW CONTROL OR ERROR REPORTING USING A READ DATA STROBE
    Publication number: 20190212920
    Abstract: A peripheral device includes a function block to provide data in response to a request from a host device, a data channel coupled with the function block to transmit the data from the function block to a host device as one or more packets, and output logic coupled with the data channel and configured to indicate validity of the data transmitted via the data channel by causing a signal to transition for each of the one or more packets of the data transmitted to the host device via the data channel, and transmit the signal to the host device.
    Type: Application
    Filed: October 15, 2018
    Publication date: July 11, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Mark Alan McClain, Qamrul Hasan, Clifford Alan Zitlaw
  • Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) device structure employing reduced processing steps
    Patent number: 10347829
    Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device with a reduced number of masking and etching steps is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate to expose a portion of the surface, and forming first spacers on sidewalls of the opening. A conductive layer is formed on the portion of the surface exposed in the opening and separated from the first spacers on the sidewalls of the opening by a gap therebetween. A bottom electrode of a ferroelectric capacitor is formed over the conductive layer and in the gap laterally of the conductive layer, a ferroelectric dielectric formed on the bottom electrode between the first spacers, and a top electrode formed on the ferroelectric dielectric.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: July 9, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, John Cronin, Tom E. Davenport
  • Combined analog architecture and functionality in a mixed-signal array
    Patent number: 10345377
    Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 9, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E. Hastings, Dennis R. Seguine
  • PRESSURE DETECTION AND MEASUREMENT WITH A FINGERPRINT SENSOR
    Publication number: 20190205604
    Abstract: A circuit, system, and method for measuring or detecting pressure or force of a fingerprint on an array of electrodes is described. Pressure or force may be measured or detected using a processed image of the fingerprint, or by measurement of capacitance of deformed variable capacitors.
    Type: Application
    Filed: December 18, 2018
    Publication date: July 4, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Andriy Ryshtun, Viktor Kremin
  • Methods and apparatus to detect a presence of a conductive object
    Patent number: 10338739
    Abstract: A method and apparatus to determine a plurality of regions, each of the plurality of regions having a detected change in sensor value that meets or exceeds a threshold value, fit a three dimensional shape to the plurality of regions, and determine a position of an object.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 2, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jonathan R Peterson, Cole D. Wilson, Thomas Fuller, Derek James Valleroy
  • Distance estimation and authentication for Bluetooth systems, and devices
    Patent number: 10341865
    Abstract: Distance estimation and authentication are provided for Bluetooth systems and devices. Proximity detection requests are transmitted using a transceiver of a tracking device. Reply messages are received from a tracked device. Designated delay values are generated, and round trip times associated with the reply messages are determined based, at least in part, on the designated delay values and time stamps associated with the reply messages. An authenticity metric associated with the tracked device is generated based, at least in part, on the round trip times.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 2, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventor: Victor Simileysky
  • USB type-C signal interface circuit
    Patent number: 10338656
    Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 2, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Karri Rajesh, Hemant Prakash Vispute, Arun Khamesra
  • Managed-NAND with embedded random-access non-volatile memory
    Patent number: 10338826
    Abstract: Systems and methods embed a random-access non-volatile memory array in a managed-NAND system to execute the boot code or other time-sensitive applications. By embedding this random-access non-volatile memory in the managed-NAND system, either on the memory controller chip or as a separate chip within the managed-NAND system package, an application may be read with fast initial access time, alleviating the slow access time limitations of NAND Flash technology. Depending on the size of the application, the system may be configured to read the whole application content or only a time-critical portion from this embedded random-access non-volatile memory array.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: July 2, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sylvain Dubois, Stephan Rosner, Clifford A. Zitlaw
  • Uniformity correction method for low cost and non-rectangular touch sensor matrices
    Publication number: 20190196653
    Abstract: Systems and methods access a correction value in a correction matrix. The correction matrix defines an active region of a touch array that includes plurality of unit cells. The correction value corresponds to a unit cell of the plurality of unit cells. Systems and methods modify a touch sense value of the unit cell using the correction value, based on the unit cell being partially within the active region. Systems and methods detect an object using the touch array, based on the modified sense value.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 27, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Andriy Yarosh, Jens Weber
  • NON-VOLATILE MEMORY DEVICE AND METHOD OF BLANK CHECK
    Publication number: 20190198125
    Abstract: A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 27, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: James Pak, Shivananda Shetty, Yoram Betser, Amichai Givant, Jonas Neo, Pawan Singh, Stefano Amato, Cindy Sun, Amir Rochman
  • NON-VOLATILE MEMORY ARRAY WITH MEMORY GATE LINE AND SOURCE LINE SCRAMBLING
    Publication number: 20190198124
    Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 27, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Yoram Betser, Kuo Tung Chang, Amichai Givant, Shivananda Shetty, Shenqing Fang
  • MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE AND METHOD OF MANUFACTURING THEREOF
    Publication number: 20190198328
    Abstract: A memory device that has a first gate disposed adjacent to a second gate and a first dielectric structure disposed between the first and second gates. The first dielectric structure has at least four layers of oxide and nitride films arranged in an alternating layer, in which each of the at least four or more layers includes a width in an approximate range of 30 ? or less. The first dielectric structure further includes a top surface that is substantially un-etched.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 27, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Shenqing Fang
  • Buried Trench Isolation in Integrated Circuits
    Publication number: 20190198611
    Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 27, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Rinji Sugino, Lei Xue, Ching-Huang LU, Simon S. Chan
  • SONOS Stack With Split Nitride Memory Layer
    Publication number: 20190198329
    Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.
    Type: Application
    Filed: January 4, 2019
    Publication date: June 27, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • REDUCING POWER CONSUMPTION IN COMPUTING DEVICES WITH WIRELESS NETWORK INTERFACES
    Publication number: 20190200291
    Abstract: An apparatus includes a wireless transceiver configured to communicate data with a network device. The apparatus also includes a processing device, operatively coupled with the wireless transceiver. The processing device is configured to determine whether a computing device coupled to the apparatus has data to transmit to the network device. The processing device is also configured to transmit a first message indicating that the computing device does not have data to transmit to the other device in response to determining that the computing device does not have data to transmit to the network device. The processing device is further configured to transition the apparatus to a reduced power state. The apparatus uses less power in the reduced power state than in an active state.
    Type: Application
    Filed: March 30, 2018
    Publication date: June 27, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Victor Simileysky, Kamesh Medapalli
  • 2T1C ferro-electric random access memory cell
    Patent number: 10332596
    Abstract: A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL1), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL2), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL1, WL2, the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 25, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Joseph S. Tandingan, Fan Chu, Shan Sun, Jesse J. Siman, Jayant Ashokkumar
  • Stochastic signal density modulation for optical transducer control
    Patent number: 10334672
    Abstract: A controller for optical transducers uses stochastic signal density modulation to reduce electromagnetic interference.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: David Van Ess, Patrick N Prendergast
  • Systems and methods for capturing noise for pattern recognition processing
    Patent number: 10332543
    Abstract: Example systems and methods capture a first plurality of portions of audio data by periodically capturing the audio data at first intervals. Embodiments detect speech onset in the audio data. Responsive to detection of the speech onset, systems and methods switch from periodically capturing the audio data to continuously capturing the audio data. Embodiments combine at least one captured portion of the first plurality of captured portions of the audio data with the continuously captured audio data to provide contiguous audio data.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 25, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Robert Zopf, Victor Simileysky, Ashutosh Pandey, Patrick Cruise
  • Memory subsystem with wrapped-to-continuous read
    Patent number: 10331359
    Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Qamrul Hasan, Shinsuke Okada, Yuichi Ise, Kai Dieffenbach, Kiyomatsu Shouji