Abstract: A smart syringe is described that is capable of measuring a position of a plunger within the barrel of the smart syringe and of communicating the status of a liquid pharmaceutical within the smart syringe to a patient database.

Abstract: A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.

Abstract: An electronic device includes a first switch configured to connect a first configuration channel (CC) terminal of a Universal Serial Bus Type-C (USB-C) controller to a VCONN supply of the USB-C controller. The first CC terminal of the USB-C controller being is to directly connect to the first CC terminal of a USB-C receptacle. The electronic device includes a second switch configured to connect a second CC terminal of the USB-C controller to a control channel physical layer logic (PHY) of the USB-C controller. The second CC terminal is to directly connect to the second CC terminal of the USB-C receptacle. The electronic device includes an overvoltage detection and protection circuit configured to deactivate the first switch or the second switch when a voltage exceeding a predetermined threshold is detected. The first switch and the second switch are each coupled to the overvoltage detection and protection circuit.

Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.

Abstract: A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.

Abstract: A modem includes a modulator and a demodulator. The demodulator includes a direct current removing (DCR) circuit to transition between an acquisition mode, where the DCR circuit operates with a first loop gain; and a tracking mode, where the DCR circuit operates with a second loop gain. The second loop gain is smaller than the first loop gain, and the timing of the transition between the acquisition mode and tracking mode is programmable.

Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.

Abstract: A device may generate network profile data indicating a set of network parameters detected by the device. The device may encrypt the network profile data and may transmit the encrypted network profile data to a network device, such as a router, or a server. The router or server may analyze the encrypted network profile data to determine if the device is secure. The router of server may perform one or more security measures if the device is not secure.

Abstract: A method and system of automatically generating source code for configuring a programmable microcontroller. The method involves displaying virtual blocks in a computerized design system where the virtual blocks correspond to programmable circuit blocks in a microcontroller chip. The user selects a user module that defines a particular function to be performed on the microcontroller. The user assigns the virtual blocks to the user module. The design system then automatically generates source code for configuring the programmable blocks to perform the desired function. The source code can then be assembled, linked and loaded into the microcontroller's memory system. When executed on the microcontroller, the executable axle will then set registers within the blocks to implement the function. Source code is automatically generated for: (1) realizing the user module in a hardware resource; and also (2) to configure the user module to behave in a prescribed manner.

Abstract: A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second gate conductor can be formed over a second gate dielectric structure, adjacent to the integrate dielectric structure. A dielectric layer can be formed over the substrate, the first and second gate conductors, and the inter-gate dielectric structure. The first gate conductor may be used to make a memory gate and the second gate conductor can be used to make a select gate of a split-gate memory cell.

Abstract: A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.

Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

Abstract: Techniques for low-power USB Type-C receivers with high DC-level shift tolerance are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to operate in presence of a VBUS charging current that is specified in a USB-PD specification.

Abstract: Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode. The cryptography block is configured to encrypt and decrypt XIP data transfers to and from a first external memory device in the XIP mode, and to encrypt and decrypt MMIO data transfers to and from a second external memory device in the MMIO mode.

Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.

Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.

Abstract: A circuit, system, and method for measuring or detecting pressure or force of a fingerprint on an array of electrodes is described. Pressure or force may be measured or detected using a processed image of the fingerprint, or by measurement of capacitance of deformed variable capacitors.

Abstract: A method includes storing a set of touch sense values corresponding to a measured characteristic of at least one unit cell of a plurality of unit cells of the touch array and accessing a correction matrix that defines an active region and an inactive region of the touch array. The inactive region is surrounded by the active region. The method further includes modifying touch sense values of a first subset of the plurality of unit cells that are partially within the active region defined by correction values of the correction matrix.

Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.