Abstract: A method includes using a memory address map, locating a first portion of an application in a first memory and loading a second portion of the application from a second memory. The method includes executing in place from the first memory the first portion of the application, during a first period, and by completion of the loading of the second portion of the application from the second memory. The method further includes executing the second portion of the application during a second period, wherein the first period precedes the second period.

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Abstract: An example apparatus provides an input signal based on sound waves received by one or more microphones. The input signal includes a voice command component and one or more interference components. The apparatus receives audio data over one or more computer networks and the audio data corresponds to the one or more interference components. The apparatus uses the audio data to remove a portion of the one or more interference components from the input signal to generate an output signal, and provides the output signal, as an estimate of the voice command component, for speech recognition.

Abstract: In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer.

Abstract: A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the first signal. The memory array including a third memory cell including a first memory gate coupled to receive a third signal. The magnitude of the third signal is different than the magnitude of the first signal and the magnitude of the second signal. The first signal, the second signal and the third signal are received concurrently.

Abstract: A capacitance sensing method includes generating a first set of currents by, for each transmit (TX) electrode of a set of TX electrodes, precharging a self capacitance of the TX electrode and a mutual capacitance between the TX electrode and a receive (RX) electrode of a set of RX electrodes by applying to the TX electrode a first excitation voltage corresponding to the TX electrode to induce a first current of the first set of currents, generating a second set of currents by, for each TX electrode, applying a reference voltage to the TX electrode to induce a second current of the second set of currents, and for each TX electrode, calculating a measure of the self capacitance of the TX electrode based on the second set of currents, and calculating a measure of the mutual capacitance between the TX electrode and each RX electrode based on the first set of currents.

Abstract: A semiconductor device comprises an embedded flash memory with row redundancy. The embedded flash memory comprises a memory bank that includes multiple physical sectors, where each physical sector comprises a plurality of erase sectors. In the memory bank, multiple portions of an additional erase sector are respectively distributed among the multiple physical sectors. The multiple portions of the additional erase sector are configured as a row-redundancy sector for the memory bank.

Abstract: Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.

Abstract: A device includes a power control analog subsystem of a universal serial bus-power delivery (USB-PD) compatible power supply device. The power control analog subsystem includes a programmable current sensing circuit and a current sense resistor coupled to the power control analog subsystem. The power control analog subsystem is configured to concurrently compare a current flow through the current sense resistor with at least three different reference values, e.g., compare a sensed voltage with at least three different reference voltages.

Abstract: A device and method that includes a shunt regulator of a universal serial bus (USB) compatible power supply device is disclosed. The shunt regulator includes an amplifier with an output, a first input, and a second input. The shunt regulator also includes a current digital-to-analog converter (DAC) that is coupled to the first input of the amplifier and a voltage bus node. The current DAC adjusts a sink or a source current delivered at the first input of the amplifier to regulate a programmable output voltage (Vbus) in the USB-compatible power supply device. The current delivered by the DAC is responsive to receipt of a digital code indicative of a programmable power supply command specifying the Vbus to be delivered by the USB-compatible power supply device on the voltage bus node.

Abstract: A method includes providing a media dataset including media content data and environmental effects metadata defining a set of environmental events each corresponding to a media timestamp of a plurality of media timestamps. The method further includes, for each environmental event in the set of environmental events, identifying a protocol timestamp for a communication protocol, where the protocol timestamp corresponds to the media timestamp of the environmental event, and generating a message for transmission according the communication protocol, where the message associates the environmental event with the protocol timestamp. The method further includes addressing the message to one or more environmental effect generators.

Abstract: A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.

Abstract: A technique for operating a capacitive sensor array is described. The technique includes measuring a first capacitance of a first set of electrodes at a first time, measuring a second capacitance of a second set of electrodes at a second time, and calculating a position of a conductive object based on a relative magnitude of the first capacitance and the second capacitance. The first set and the second set includes at least one electrode in common and at least one electrode that is not in common.

Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasm oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.

Abstract: A method of forming a vertical non-volatile (NV) memory device such as 3-D NAND flash memory includes forming a vertical NV memory cell string within an opening disposed in a stack of alternating layers of a first layer and a second layer over a substrate, and dividing the vertical NV memory cell string into two halves with a first vertical deep trench and an isolation dielectric pillar formed in the first vertical deep trench, such that memory bit density of the divided vertical NV memory cell strings double the memory bits of the device.

Abstract: A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.

Abstract: Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture. If the read data strobe signal is not received before expiration of a predetermined maximum latency time, the peripheral controller is indicating a read data error back to the host.

Abstract: Disclosed herein are system, methods, and apparatus for low power capacitive sensors. Apparatus may include a timing block configured to generate a repetitive trigger signal having a first frequency, and further configured to generate a clock signal having a second frequency. Apparatus may also include a sensing block coupled with the timing block and configured to, in response to the repetitive trigger signal, detect a change in capacitance associated with an object proximate to a capacitive sensor button by applying an excitation signal to the capacitive sensor button during a measurement period. Apparatus further include a wake logic block coupled with the sensing block and configured to transition a processing unit from a first power consumption state to a second power consumption state in response to the sensing block detecting the change in capacitance associated with the object proximate to the capacitive sensor button.

Abstract: A method of making a semiconductor device is provided. The method includes forming a deep well (DWELL) and a well (WELL) in a first region of a substrate, the WELL adjacent a surface of the substrate so that an interface between the WELL and DWELL is exposed on the surface of the substrate. A channel for a DEMOS transistor is formed in the first region over the interface and includes a first channel formed in the WELL and a second channel formed in the DWELL. A gate layer is deposited and patterned to concurrently form in the first region a first gate for the DEMOS transistor and in a second region a second gate for an ESD device. Dopants are implanted in the first and second regions to concurrently form a drain extension of the DEMOS transistor, and an ESD diffusion region of the ESD device.

Abstract: A method includes using a direct memory access controller, transferring first data from a memory to an input/output control circuit via a first bus and transferring the first data from the input/output control circuit to an authentication processing circuit via a second bus, without using the first bus. The method includes using the authentication processing circuit, generating authentication data based on the first data and transferring the first data from the input/output control circuit to a cryptography processing circuit via a third bus, without using the first bus. Responsive to authentication of the first data by a first CPU coupled to the first bus, the method includes using the cryptography processing circuit, decrypting the first data, and using the direct memory access controller, transferring the decrypted first data from the input/output control circuit to the memory via the first bus.