Abstract: A capacitance sensing circuit may include a charge to digital converter, coupled to a signal receiver channel, to receive a signal from a capacitive sense array. The capacitance sensing circuit may also include a baseline compensation signal generator, coupled to the signal receiver channel, to provide a baseline compensation signal in an opposite phase of the signal to the signal receiver channel.

Abstract: A memory apparatus that has at least two non-volatile memory (NVM) cells disposed side by side overlying a substrate and an isolation structure disposed between the first and second NVM cells in the substrate. The first and second NVM cells share a common charge trapping layer that includes a continuous structure, and the portion of the common charge trapping layer that is disposed directly above the isolation structure includes a higher oxygen and/or nitrogen concentration than the portions of the common charge trapping layer that are disposed within the first and second NVM cells.

Abstract: A sensor-compatible overlay is disclosed which uses anisotropic conductive material to increase capacitive coupling of a conductive object through the overlay material to a capacitive sensor. The anisotropic conductive material has increased conductivity in a direction orthogonal to the capacitive sensor. In one embodiment, the overlay is configured to enclose a device which includes a capacitive sensor. In another embodiment, the overlay is configured as a glove.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

Abstract: Disclosed is a method for responding to a single user read command of a complementary cell array including one or more complementary cell pairs, the method including: determining if a first group of cells out of a data word is in an erased state or in a programmed state, and outputting a data word so that (a) if the first group of cells is determined to be erased a logical “one” is output for each bit of the data word and (b) if the first group of cells is determined to be programmed the result of a complementary read is output for each bit of the data word.

Abstract: In a reliable multi-cast, a concealment scheme may be applied to recover or conceal lost or otherwise corrupted packets of audio information for one channel based on the audio information of other channels in the reliable multi-cast.

Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.

Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Abstract: An integrated circuit device can include at least one input; at least one output configured to provide a multi-bit output value; at least one input; at least one output configured to provide a multi-bit output value; a plurality of configurable digital filter circuits; and switch circuits coupled to the at least one input and to the at least one output, the switch circuits configurable to connect same digital filter circuits as a single processing path or separate processing paths.

Abstract: A modem includes a modulator and a demodulator. The demodulator includes a direct current removing (DCR) circuit to transition between an acquisition mode, where the DCR circuit operates with a first loop gain; and a tracking mode, where the DCR circuit operates with a second loop gain. The second loop gain is smaller than the first loop gain, and the timing of the transition between the acquisition mode and tracking mode is programmable.

Abstract: A capacitive sensor includes a switching capacitor circuit, a comparator, and a charge dissipation circuit. The switching capacitor circuit reciprocally couples a sensing capacitor in series with a modulation capacitor during a first switching phase and discharges the sensing capacitor during a second switching phase. The comparator is coupled to compare a voltage potential on the modulation capacitor to a reference and to generate a modulation signal in response. The charge dissipation circuit is coupled to the modulation capacitor to selectively discharge the modulation capacitor in response to the modulation signal.

Abstract: A method includes storing a set of touch sense values corresponding to a measured characteristic of at least one unit cell of a plurality of unit cells of the touch array and accessing a correction matrix that defines an active region and an inactive region of the touch array. The inactive region is surrounded by the active region. The method further includes modifying touch sense values of a first subset of the plurality of unit cells that are partially within the active region defined by correction values of the correction matrix.

Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

Abstract: An example semiconductor chip includes analog circuits, digital circuits, and a digital input port. The digital input port is to receive an input signal. The analog circuit is to receive the input signal from the digital input port and produce a digital signal based on the input signal.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for booting an application from multiple memories. An embodiment operates by executing in place from a first memory a first portion of the application, loading a second portion of the application from a second memory, and executing the second portion of the application.

Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.

Abstract: A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.