Abstract: In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.

Abstract: Dynamic bandwidth selection based on environmental conditions is described. A bandwidth of a sub-bandwidth may be selected based on signal strength, channel interference, or overlap to optimize throughput and/or energy per bit. Additionally, system power level may define a communication bandwidth.

Abstract: In an example embodiment, a device comprises a gate driver and a current detector circuit. The gate driver is configured to be coupled to a power switch on the VBUS line of a USB connector. The current detector circuit is configured to be coupled to the VBUS line and comprises a current sense amplifier, a reference voltage generator circuit, and a comparator. The current sense amplifier is configured to receive a pair of input voltages and to output an indicator signal responsive to the input voltage difference. The reference voltage generator circuit comprises a digital-to-analog converter configured to generate a reference voltage signal based on a received voltage selector signal that is a binary input signal comprising multiple bit values. The comparator is configured to receive the indicator signal and the reference voltage signal and to output an interrupt signal responsive to the indicator signal exceeding the reference voltage signal.

Abstract: Example systems, methods, and apparatus transfer data to a communication device by capacitively coupling an analog signal through a capacitor formed by the capacitance sensor, of a transmitting device, and the communication device

Abstract: A protecting circuit includes a discharge switch, a trigger circuit, and a shunt circuit. The discharge switch is connected between a first terminal and a second terminal. The trigger circuit is connected to the discharge switch and comprises load devices, connected in series between the first terminal and the second terminal, and a first node between a first one and a second one of the load devices. The shunt circuit is connected to the trigger circuit at the first node, where the shunt circuit comprises a shunt switch and a shunt pathway that is connected between the first node and the shunt switch.

Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

Abstract: A capacitive fingerprint sensor includes a set of capacitive sensor electrodes in a sensing area. The set of capacitive sensor electrodes includes a set of transmit (Tx) sensor electrodes, a set of receive (Rx) sensor electrodes, and a set of compensation electrodes. The fingerprint sensor also includes a multiphase capacitance sensor that is configured to perform a sensing scan of the capacitive sensor electrodes by applying a first Tx signal to a first subset of the Tx sensor electrodes while simultaneously applying a second Tx signal to a second subset of the set of Tx sensor electrodes, and based on a compensation signal received at the set of compensation electrodes, reduce a component of the Rx signal originating from a source other than a contact at the sensing area.

Abstract: Disclosed herein is an apparatus that includes a ferrocapacitor disposed on a damascene barrier film. The damascene barrier film includes a hydrogen barrier region and an oxygen barrier region, with each being in contact with a bottom surface of the ferrocapacitor.

Abstract: An Internet-of-Things (IoT) device and secure communication and authentication protocol is described for identifying an IoT device and counter party and ensuring that communication between the IoT device and the counter party is authenticated before transmission and receipt of data over the trusted communication pathway.

Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. The method begins with depositing and patterning a first photoresist mask over a surface of a substrate to expose a N-SONOS region, and implanting a channel for a NSONOS device through a first pad oxide, followed by depositing and patterning a second photoresist mask to expose a P-SONOS region, and implanting a channel for a PSONOS device through a second pad oxide. Next, a number of Nwells are concurrently implanted for the PSONOS device and a PMOS device in a core region of the substrate. Finally, the first and second pad oxides, which were left in place to separate the P-SONOS region and the N-SONOS region from the first and second photoresist masks, are concurrently removed. In one embodiment, implanting the Nwells includes implanting a single, contiguous deep Nwell for the PSONOS and PMOS device.

Abstract: A memory device that includes a non-volatile memory (NVM) transistor disposed in a first region of a substrate. The NVM transistor includes a first gate including a first type of conductor material. The memory device further includes a first type of low voltage field-effect transistor (LV FET) and an input/out field-effect transistor (I/O FET) disposed in a second region of the substrate. The LV FET includes a second gate comprising a second type of conductor material, the I/O FET includes a third gate comprising a second type of conductor material, and the first and second conductor materials are different. Other embodiments are also described.

Abstract: A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the buried trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Abstract: One embodiment includes and I/0 bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/0 port to the signal line. Switch logic coupled to the I/0 bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/0 port.

Abstract: Techniques for multi-phase self-capacitance (MPSC) scanning of a sensor array are described herein. In an example embodiment, a device comprises a sensor logic coupled to a processing logic. The sensor logic is configured to concurrently sense multiple sensor elements of the sensor array in each of multiple scanning operations in order to obtain multiple measurements, where each measurement represents a collective charge of the multiple sensor elements accumulated during a corresponding scanning operation. The processing logic is configured to determine data values based on the obtained multiple measurements, where the data values respectively represent self-capacitances of the multiple sensor elements.

Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

Abstract: Apparatuses and methods of distinguishing between a finger and stylus proximate to a touch surface are described. One apparatus includes a first circuit to obtain capacitance measurements of sense elements when a conductive object is proximate to a touch surface. The apparatus also includes a second circuit coupled to the first circuit. The second circuit is operable to detect whether the conductive object activates the first sense element, second sense element, or both, in view of the capacitance measurements. To distinguish between a stylus and a finger as the conductive object, the second circuit determines the conductive object as being the stylus when the second sense element is activated and the first sense element is not activated and determines the conductive object as being the finger when the first sense element and the second sense element are activated.

Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel to the first surface, and top surfaces of the select gate and memory gate are approximately at or below an elevation of the planarized surface of the metal-gate. Generally, at least one of the top surfaces of the select gate or the memory gate includes a silicide formed thereon. Other embodiments are also disclosed.

Abstract: The sensing circuit includes including first input of a first electrode, a first set of inputs of a first set of two or more electrodes forming a first intersection and a second intersection, and a second set of inputs of a second set of two or more electrodes forming the second intersection and a third intersection. The sensing circuit includes a scan control circuit, coupled to the touch panel of electrodes, to concurrently select the sets of electrodes via a multiplexer. The touch sensing circuit includes an analog front end configured to generate digital values representative of mutual capacitances of a first and second unit cell, wherein the first unit cell comprises the first and second intersections and the second unit cell comprises the second and third intersections, and a channel engine configured to generate capacitance values corresponding to the unit cells.