Abstract: A phase controller includes a plurality of pulse width modulation (PWM) circuits, a plurality of switching devices, a computing unit, and a latency generator. The plurality of PWM circuits output pulse signals. The plurality of switching devices are coupled to the respective plurality of PWM circuits, and switch on and off based on the pulse signals. The computing unit calculates the pulse signals to be output from the plurality of PWM circuits, based on outputs of the plurality of switching devices. The latency generator generates latency in any of the pulse signals so that edge positions of the pulse signals output from the plurality of PWM circuits do not collide with each other, wherein the pulse signals change values at the edge positions.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

Abstract: A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal.

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Abstract: A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Abstract: Semiconductor devices including non-volatile memory devices and methods of fabricating the same are provided. Generally, the memory device includes a gate structure, a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. In one embodiment, the multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide, and the first and the second dielectric layers include a nitride. Other embodiments are also disclosed.

Abstract: An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB. The second type of EBs store system management information and the third type of EBs store user data. When the flash memory is started up, the overlaid EB mapping scheme scans the corresponding portion to locate the first type of EB, locates the system EBs using the pointers, and locates the data EBs using the system management information.

Abstract: Source tracking for phased array systems is described herein. One processing device includes a transceiver to transmit or receive radio frequency (RF) signals via a plurality of antenna elements and a processor coupled to the transceiver. The processor executes a multi-angle source-tracking tool configured to determine and store a set of angle estimation values of an angle between the plurality of antenna elements and the second antenna, a set of confidence measurements, and at least one of an Area-of-Arrival (ARoA) value or an Area-of-Departure (ARoD) value based on the RF signals. Each of the set of confidence measurements indicates a confidence of an angle estimation value of the set of angle estimation values.

Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.

Abstract: A circuit, system, and method for converting mutual capacitance to a digital value is described. Charge packets are transferred from a mutual capacitance to a pair of integration capacitors during alternate charge and discharge cycles. The time required to bring the discharged integration capacitor to the same potential as the charged integration capacitor with a current source is measured as a single-slope analog-to-digital converter (ADC). The output of the ADC is representative of the mutual capacitance.

Abstract: Apparatuses and methods of converting a capacitance measured on a sense element to a digital value are described. One apparatus includes a modulator having a modulator capacitor, a sense element selectively coupled in a feedback loop of the modulator to operate as a switching capacitor. The apparatus also includes a first switch coupled between a voltage source and a first node of the switching capacitor and a second switch coupled between the first node of the switching capacitor and a first node of the modulator capacitor. The switching capacitor provides a charge current to the modulator capacitor via the second switch. The modulator measures a capacitance of the sense element and converts the measured capacitance to a digital code representing the capacitance.

Abstract: A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Abstract: Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode. The cryptography block is configured to encrypt and decrypt XIP data transfers to and from a first external memory device in the XIP mode, and to encrypt and decrypt MMIO data transfers to and from a second external memory device in the MMIO mode.

Abstract: An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.

Abstract: A device includes a security controller to determine whether a wireless security device is authorized to access at least one resource protected by a secure access device based, at least in part, on identification signals that originate from the wireless security device. The security controller is configured to receive location information corresponding to the wireless security device from at least one wireless device. When the wireless security device is authorized to access at least one resource, the security controller is configured to direct the security access device to disable at least one security measure that restricts user access to the at least one resource based, at least in part, on the location information corresponding to the wireless security device.

Abstract: Methods and apparatus include and amplifier circuit and a first capacitor branch including a first plurality of capacitors. The first capacitor branch couples to an input signal and to an input of the amplifier circuit. A second capacitor branch includes a second plurality of capacitors. The second capacitor branch couples to the input of the amplifier circuit and to an output of the amplifier circuit.

Abstract: A memory device can include an interface comprising a plurality of control and address connections and at least one set of data connections; memory circuits comprising a plurality of storage locations randomly accessible for read and write operations in response to an address value received on the address connections; and accelerator circuits coupled to the memory circuits and configured to perform at least one predetermined operation on data stored in the memory device to generate modified data for storage within the memory circuits in response to at least one command received on the interface; wherein the at least one command is supplemental to read and write commands executable by the memory device.

Abstract: Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.

Abstract: Disclosed herein are an apparatus for controlling a switch-mode power supply, and a method of operating the same. In an embodiment, it is determined whether or not a current of an inductor of the switching power supply has become less than or equal to a predetermined value. In an embodiment, a variable reference voltage is adjusted based on the current of the inductor and an output voltage. In an embodiment, a switch is turned off based on the inductor current, the output voltage, and the variable reference voltage.