Abstract: Circuits and methods to design and to fabricate said circuits to accomplish a two-level DRAM cell or a multilevel DRAM cell using a natural transistor have been achieved. The usage of a natural transistor, having a threshold voltage of close to zero, as a pass transistor reduces the amount of current required for a read operation significantly. The usage of a natural transistor in a multi-level DRAM is enabling to implement easily a high number of voltage levels, and thus more information, in one DRAM cell and is reducing the amount of output current required as well. The fabrication of said DRAM cells in an integrated circuit, comprising a natural transistor and standard transistors, include masking of the natural transistor during the ion implantation to avoid impurities increasing the threshold voltage.

Abstract: The current mirror configuration includes four branches, a biasing branch, a first comparator branch, a second comparator branch and a measurement branch. The measurement branch is connected to a pad of the IC device and a measurement current is charged on to the pad. The measurement current is mirrored from the current of the biasing branch and the measurement current is mirrored to the second comparator branch. The biasing branch is mirrored to the first comparator branch using a scale that the current of the first comparator branch is smaller than the current of the biasing branch. In case of a short-circuit, the current of the measurement branch is larger than the current of the first comparator branch.

Abstract: The present invention is related to methods and systems for detecting defective imaging array pixels and providing correction, thereby reducing or eliminating visible image artifacts. One embodiment of the present invention provides an on-line bad pixel detection and correction process that compares a first pixel readout value with a first value related to the readout values of other pixels in first pixel's local neighborhood. When the first pixel readout value varies by more than a first amount as compared with the first value, a second value related to the readout values of the neighboring pixels is used in place of the first pixel readout value.

Abstract: This invention provides a circuit and a method for interfacing a subscriber information module, SIM to a base band controller for a mobile phone. It provides voltage level shifting to allow a low voltage base band controller chip to interface to a higher voltage SIM card. The higher voltage bus goes to the SIM card of a mobile phone. The subscriber information module typically contains personal information such as telephone number, identification codes and pin numbers. The circuit of this invention uses active transistor pull-down and pull-up mechanisms. The active pull-up is active for less than one bit time so that the SIM card sees only a 20 kilo ohm resistor allowing performances equal to or better than ISO7816 specifications.

Abstract: A circuit and method are given, which realizes a stable yet sensitive differential capacitance measuring device with good RF-suppression and with very acceptable noise features for use in capacitive sensor evaluation systems. By evaluating the difference of capacitor values only—with the help of a switched capacitor front-end—large spreads of transducer capacitor values are tolerable. Furthermore a mode of operation can be set up, where no essential galvanic connection between sensor input and the active read-out input at any given time is existing. The solution found exhibits a highly symmetrical construction. Using the intrinsic advantages of that solution the circuit of the invention is manufactured as an integrated circuit with standard CMOS technology at low cost.

Abstract: The domino asynchronous successive approximation (ASA) analog-to-digital converter (ADC) converts an analog signal to an n-bits digital signal. The domino ASA ADC is made out of n-blocks, corresponding to the number of n-bits of the digital output. Each of these n-blocks generates a conversion bit and calibrates all following blocks, comparable to a domino structure. One key advantage of the domino ASA ADC is its modular structure; each block is independent from all others. The unity capacitors used need to be matched only within their specific blocks. The architecture is very flexible; it is possible to increase the resolution by adding more blocks of the same kind. The ASA ADC is very fast, its speed is only limited the RC constants during the sampling and measurement phase and the speed of the comparators used.

Abstract: A method for tracking the MOS oxide thickness by the native threshold voltage of a “native” MOS transistor without channel implantation for the purpose of compensating MOS capacitance variations is achieved. The invention makes use of the fact that in MOS devices the threshold voltage is proportionally correlated to the oxide thickness of said MOS device. The threshold voltage can therefore be used to build a reference voltage Vx+Vth which accurately tracks the MOS capacitance variations in integrated circuits. Circuits are achieved to create a frequency reference and a capacitance reference using said method Additionally a method is introduced to create a capacitance reference in integrated circuits using said MOSFET capacitors.

Abstract: In a translinear amplifier, where the output voltage difference is kept at the same relative difference as the input voltage difference and which is normally formed by two current balancing circuits and some form of an amplifier stage, said amplifier stage is drastically simplified and even replaced by a simple diode. Two additional functions sharply limit the analog operating region: an added current limiting transistor on one side and the purpose use of the voltage limited by the power supply on the other side. One key objective is linearly switching on or off a transistor, and getting sharp maxima and minima of its RDSon at the extreme ends.

Abstract: A circuit and a method to measure continuously the resistance of variable resistors in series as e.g. potentiometers within a sensor, used for e.g. a joystick, has been achieved. The voltage across said sensor comprising any number of variable resistors is stabilized. A constant current source is providing a minimum current through said sensor. A variable current source is used to zoom variations of current through the sensor caused by variations of resistance of the sensor. Said variable current is mirrored and by measuring the voltage across a shunt resistor the total resistance of the sensor is identified. Using ports between each of the resistors, voltages can be measured representing the resistance of each of the variable resistors using known equations of voltage dividers. Any number of variable resistors can be used in the circuit invented.

Abstract: A method and a circuit for avoiding memory access collisions during asynchronous read-write access to a single-port RAM (SPRAM) are described. Serial write access by means of a serial interface and read access with a read strobe from an independent read device are generated asynchronously. Prerequisites for the implementation are: firstly, use of a serial interface providing a serial clock signal; secondly, write access to SPRAM has to occur at the end of serial transmission; thirdly, a write strobe impulse has to be short compared to the original read strobe. Energy saving is achieved by guaranteeing only one regular read strobe, even when multiple write accesses occur during one read access. The read strobe signal can therefore be used also for control of an LCD backplane counter.

Abstract: A circuit and a method for an effective way to customize the display driver software of any type of LCD-display and any type of LCD-driver chip used in an LCD display system is achieved. This is important in a multiple sourcing environment where LCD driver chips and LCD modules from different vendors are used in LCD display systems. This is accomplished through identification and registration of the information relevant for the said software customization by storing said information in an LCD module identification register. A microprocessor controlling the LCD display system is reading this identification register and providing the software customization elements specific to the LCD-driver chip and to the LCD-module during an initialization step of the system.

Abstract: A CMOS pixel responsive to different colors of optical radiation without the use of color filters is described. A deep N well is formed in a P type silicon substrate. An N well is then formed at the outer periphery of the deep N well to form a P well within an N well structure. Two N+ regions are formed in the P well and at least one P+ region is formed in the N well. A layer of gate oxide and a polysilicon electrode is then formed over one of the N+ regions. The PN junction between the deep N well and the P type silicon substrate is responsive to red light. The PN junction between the deep N well and the P well is responsive to red light. The PN junction between the P well and the N+ region which is not covered by polysilicon and the PN junction formed by the N well and the P+ region are responsive to green or blue light. The PN junction formed by the junction between the P well and the N+ region which is covered by polysilicon is responsive to green light.

Abstract: An imaging method and system that flexibly accesses light sensor elements and processes imaging signals. The imaging system comprises an array of pixel sensor cells, an array controller and a readout control circuit.

Abstract: Methods and structures to reduce in semiconductor packages the length of critical electrical connections between bond pads on one or multiple semiconductor chips and wire landing pads on a substrate have been achieved. An electrical connection becomes critical if high current, high speed or radio frequency signals have to be transported. Moving the wire landing pads of critical connections on the substrate closer to the semiconductor chip utilizing unpopulated spaces of an array grid design reduces the length of said wires. This could be a ball grid array (BGA) or any other kind of grid array. Said methods and structures invented are applicable to single-chip modules and to multi-chip modules. The design of the grid array has to be modified to provide free spaces for the wire landing pads of critical electrical connections within the grid array close to the semiconductor chip as required by the design rules. The design change can be done without increasing the number of solder balls or solder pins, etc.

Abstract: A circuit where the same amplifiers and the same volume adjustment circuitry are used for the ringer mode as well as for the audio mode of a mobile phone is achieved. The volume adjustment in the audio and ringer mode is provided by a precise amplitude setting via the gain control stages of an inverting voltage amplifier used in a bridge circuit through a current-voltage conversion. This volume adjustment circuit avoids the high power dissipation of a volume control through pulse width modulation (PWM) and avoids the risk of over-and undershooting of the amplifier's output signal due to a high slew rate in combination with the inductance of the loudspeaker. The current-voltage conversion is performed by a series of resistors activated by a series of correspondent switches. High impedance current less sense paths are eliminating the parasitic effect of the resistance of low cost standard switches to adjust the volume of the loudspeaker in the audio and the ringer mode.

Abstract: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N? well. The N? well is in a P? type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N? well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N? well potential so that they remain reverse biased with respect to the N? well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N? well forms a second gate for the dual gate PMOS transistor since the potential of the N? well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible.

Abstract: Five circuit topologies of Voltage-Controlled Oscillators with Single Inductor (VCO-1L) are proposed. They offer lower power consumption, higher output amplitude, broader tuning range, cleaner s-rum and higher frequency stability seen as lower phase-noise. Most of the achievements are based on the development of active pull-down control circuitries of the timing and active charge dissipation in the transistors. The applications of the present invention are of critical importance for wireless communication systems not allowing any limitations in the frequency range. Among them are base stations and mobile terminals mobile phones, GSM, PCS/DCS, W-CDMA etc., as well BlueTooth, Wireless LAN, Automotive and ISM band etc. The advanced performance of the circuits is based on important architectural specifics and proven by simulation on advanced CMOS process.

Abstract: A method and a circuit to achieve a low drop-out voltage regulator with a wide output load range has been achieved. A fast loop is introduced in the circuit. The circuit is internally compensated and uses a capacitor to ensure that the internal pole is more dominant than the output pole as in standard Miller compensation. The quiescent current is set being proportional to the output load current. No explicit low power drive stage is required. The whole output range is covered by one output drive stage. By that means the total consumption of quiescent or wasted current is reduced. An excellent PSRR is achieved due to load dependent bias current.

Abstract: In a Class-D Amplifier with PCM (Pulse Code Modulated) input signal, the output pulse width may be adjusted to provide a constant time-voltage-area or the output pulse width may have one of several discrete values to provide a multi-level output system. A fundamental idea of this disclosure is to assure the center of each output pulse is always positioned at the nominal clock or with a fixed delay relative to the nominal clock. Said Class-D Amplifier typically converts the input signal into PDM (Pulse Density Modulated) pulses with a Sigma Delta Modulator and typically drives the output load with an H-Bridge.

Abstract: A motor bridge driver interface, implemented in an ASIC using cost-efficient CMOS technology, is designed to control four external MOS power transistors in a H-bridge configuration for DC-motor driving to achieve accurate and fast switching. Main components of the -interface are comprising a charge pump for generating the control voltage for the high-side N-channel MOS transistors, high-side (HSD) circuits, low-side (LSD) circuits and a complex digital interface for supplying the control signals in a programmable timing scheme. A “strong” charge pump is used to realize a simple CMOS switch to steer the output to the high-side transistors of said H-bridge. The motor bridge is connected to the battery supply by an additional N-channel MOS transistor to implement a reverse supply protection.