Abstract: A method to linearize the characteristic of a Class-D amplifier is achieved, by compensating for the pulse-area-error, caused by a non-constant power-supply and similar circuit inconsistencies. A Class-D Amplifier typically converts the PDM (Pulse Density Modulated) input signal with a Sigma Delta Modulator and typically uses an H-Bridge as the Class-D power output stage. A fundamental idea is to keep the time-voltage area of every pulse constant. To achieve this, the circuit integrates the power supply voltage, starting with the PDM input pulse and stopping, when the defined time-voltage reference is reached. To compensate not only for power supply variations, but also for e.g. the voltage drop across the output devices, the integrator's input would be more directly referenced to the actual voltage across the output load.

Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.

Abstract: A multiple level logic memory device is achieved. The device comprises, first, a plurality of memory cells capable of storing an analog voltage. Second, there is included a means of converting an external data word value comprising one value of a set of at least three possible values into a writing analog voltage corresponding to the external data word value. Third, a means of decoding an external address value in response to a write command such that the writing analog voltage is electrically coupled to the memory cell is included. Fourth, there is included a means of converting the memory cell analog voltage into an external data word value comprising one value of the set of at least three possible values corresponding to the memory cell analog voltage. Finally, a means of encoding the external address value in response to a read command such that the memory cell analog voltage is electrically coupled to the means of converting the memory cell analog voltage is used.

Abstract: This invention provides a method and an apparatus for saving power dissipation during the testing and evaluation of liquid crystal display LCD panels. In addition, this invention provides a method and apparatus of the changing of the order of backplane and segment addressing to reduce the power consumed by LCD panels. The method includes the step of interlacing the access of common or backplane addresses to an LCD. The LCD power saving method also includes the interlacing the access of the RAM data driving the LCD segment drivers. The segment address signals are developed from data read out of a random access memory, RAM. The segment address signals are activated such that alternating LCD panel locations are written with ones and zeros in a checkerboard pattern so as to stress the LCD panel in the worst case. This method provides for the saving of power dissipation during testing and evaluation by reducing the amount of segment switching from once every backplane cycle to once every frame.

Abstract: This invention provides a method and an apparatus for power reduction for LCD drivers using backplane charge sharing. In addition, this invention relates to the use of switches between adjacent backplane drivers in order to transmit and reuse the discharged charge from one backplane's capacitance in order to charge the capacitance of an adjacent backplane. One embodiment of this invention utilizes N metal oxide semiconductor field effect transistors, NMOS-FETs to implement the switch connection between adjacent backplane drivers.

Abstract: A method to generate virtual multi-level output pulses for a Class-D Amplifier, where the time-voltage-area corresponds to a multiple of digital levels is achieved. A class-D Amplifier using PDM (Pulse Density Modulation) normally converts the input signal with a Sigma Delta Modulator into high-frequency pulses of equal width and typically drives an H-Bridge, with its 3 physical output levels. The disclosed invention however adds the methods to produce pulses with a multiple of discrete values of width and provides the method to generate a pulse length select control signal for these variable-width-pulses. Using multi-level pulse widths, in contrast to just a single pulse width, allows the reduction of the pulse-sampling rate by the same factor. Or Multi-level pulse widths allow a better quality output signal. In addition, better power efficiency is achievable.

Abstract: A method and a circuit for avoiding memory access collisions during asynchronous read-write access to a single-port RAM (SPRAM) are described. Serial write access by means of a serial interface and read access with a read strobe from an independent read device are generated asynchronously. Prerequisites for the implementation are: firstly, use of a serial interface providing a serial clock signal; secondly, write access to SPRAM has to occur at the end of serial transmission; thirdly, a write strobe impulse has to be short compared to the original read strobe. Energy saving is achieved by guaranteeing only one regular read strobe, even when multiple write accesses occur during one read access. The read strobe signal can therefore be used also for control of an LCD backplane counter.

Abstract: A method for compensating for the pulse area error of a Class-D power amplifier is achieved; especially it compensates the variations in the supply voltage and similar dependencies. A Class-D Amplifier typically gets pulse coded digital input (PCM) and may comprise a Sigma Delta Modulator to generate the signals driving the power output stage, typically an H-Bridge. A fundamental idea of this invention is to measure the real area of the output pulses, where the area is defined as the pulse duration multiplied by the pulse voltage amplitude, and to compare it with the ideal nominal pulse area. The pulse area error is calculated and then subtracted from said amplifier's input data. Key element of this invention is the “Pulse Area Compensation Function”, which calculates said real pulse area (voltage amplitude multiplied by time), compares said real pulse area with said ideal pulse area and feeds the difference into the input of said Sigma Delta Modulator.

Abstract: A method for a fast color saturation control of digital color images using one color saturation factor has been achieved. Said method can be performed in any color space having three primaries as e.g. the R-G-B or in the CMY color space without the requirement to convert all the pixels of said color image into another color space as e.g. HSI to perform the color saturation control. Thus a significant computational effort for the conversion of the pixels from one color space into another and back can be avoided. Saving computational effort saves time and reduces the electrical power consumption. Right after the color saturation control process the corrected images can be viewed, if the colors are not satisfactory the process can be easily repeated using a modified color saturation factor. Said method can be used for new pictures taken by a digital camera as well as for downloaded pictures from any source. Additionally said method of color saturation control can be combined with a color correction process.

Abstract: The invention refers to a charge/discharge protection circuit for a rechargeable battery which is protected by a fusible link, where the rechargeable battery comprises a control logic which opens or closes a load switch depending on the magnitude of the battery voltage, the voltage on the charge/discharge terminals of the protection circuit and the charge/discharge current. The protection circuit is designed so that the electric strength needs to match only the actual maximum battery voltage, thus requiring little real estate on an IC chip and also allowing most components to be integrated.

Abstract: A battery protection circuit for use between a battery output and a load is achieved. The circuit comprises, first, a plurality of fused cells coupled in parallel between the battery output and the load. Each fused cell comprises, first, a fuse having first and second terminals where the first terminal is coupled to a battery output. Second, a means having zener effect has a p terminal and an n terminal. The p terminal is coupled to the second terminal of the fuse. Finally, a cell switch having first and second terminals completes each fused cell. The cell switch first terminal is coupled to the second terminal of the fuse, and the cell switch second terminal is coupled to the n terminal of the diode to form a cell output. Finally, the battery protection circuit comprises a shorting switch, that may comprise a MOS transistor that exhibits punch through, that is coupled between the load and each fused cell output. The current source second terminal is coupled to ground.

Abstract: A new floating gate programmable device cell is achieved. The device comprises, first, a negative injection transistor having drain, source, bulk, and gate. The source and bulk are coupled to ground. The drain forms an output of the cell. A positive injection transistor has drain, source, bulk, and gate. The drain, source, and bulk are coupled to a programming voltage. The gate is coupled to the negative injection transistor gate to form a floating gate node. Finally, a capacitor has a first terminal coupled to the floating gate node and a second terminal coupled to a control voltage. The states of the programming voltage and the control voltage determine negative charge injection onto the floating gate node and positive charge injection onto the floating gate node. A voltage on the floating gate node comprises a nonvolatile memory state that is detectable by the impedance of the output.

Abstract: A method for regulating the battery charge current with improved loop stability is achieved. Key element of this invention is a digital low pass filter within the feedback loop of the regulator, which is built by an up/down counter, a digital-to-analog-converter and a variable frequency oscillator. To achieve regulating loop stability in state-of-the-art analog designs, the dominant pole has to be selected at a sufficiently low frequency, which causes the regulator to be too slow for pulsed charge currents. The disclosed invention replaces the analog feedback circuit with a digital low pass filter arrangement. It achieves stability by being able to choose the low pass filter time constant longer than the supply-voltage-pulse-width with reduced circuit complexity and less electronic circuit resources. Furthermore, the timing characteristics can be varied during normal operation by modifying the oscillator frequency and by presetting the up/down counter to defined values.

Abstract: A method for dynamically adapting the biasing current for a fast switching voltage comparator is achieved. The difference of the two input signals of said comparator controls the comparator's biasing current, where the biasing current is high only when the difference is low and the comparator's switching is likely to happen and where the biasing current is kept low at other times. In a current mirroring circuit, the voltage difference at the comparator inputs controls the mirroring ratio. The biasing current reaches its maximum when the input voltage difference approaches zero. Once the input voltage difference crosses zero and continues to change in the same direction as before, that is after the polarity of the voltage difference changed, the control mechanism alternates the connection of the input signals to the current controlling elements, in order to now reduce the current with a further increase of the voltage difference.

Abstract: A method for regulating the battery charge current with improved loop stability is achieved. Key element of this invention is a digital low pass filter within the feedback loop of the regulator, which is built by an up/down counter, a digital-to-analog-converter and a variable frequency oscillator. To achieve regulating loop stability in state-of-the-art analog designs, the dominant pole has to be selected at a sufficiently low frequency, which causes the regulator to be too slow for pulsed charge currents. The disclosed invention replaces the analog feedback circuit with a digital low pass filter arrangement. It achieves stability by being able to choose the low pass filter time constant longer than the supply-voltage-pulse-width with reduced circuit complexity and less electronic circuit resources. Furthermore, the timing characteristics can be varied during normal operation by modifying the oscillator frequency and by presetting the up/down counter to defined values.

Abstract: The invention refers to a charge/discharge protection circuit for a rechargeable battery being able to differentiate between a temporary overvoltage on the charge/discharge terminals and a permanent overvoltage and in the last case for security reasons to permanently disconnect the battery from the charge/discharge terminals. Hereby said protection circuit comprises a number of partial switches (15[1:]), being either parallel to a load switch (LS) or parallel to the charge terminals, and an overvoltage detector (10) which closes in case of an overvoltage all partial switches via a control logic (11, 12, 13, 17, 18) and which afterwards opens one partial switch after the other. A voltage detector (16), monitoring the remaining voltage over the partial switches, inhibits, however, the opening of at that time next partial switch if the remaining voltage over the still closed partial switches is higher than a predefined limit of said remaining voltage.

Abstract: The invention refers to a charge/discharge protection circuit for a rechargeable battery, where the protection circuit is integrated on a single chip, including the fusible link, the load current switch and the short-circuit switch. This is achieved by dividing the functions of the fusible link, the load current switch, and the short-circuit switch into in parallel arranged T-sections, each of which is designed for only a fraction of the nominal load so that each of the easily integrated fuse segments carry only the respective fraction of the nominal current. It is important that the entire protection circuit or its control logic will not be destroyed before through an unduly high over-voltage, in which case the sequential melting of the fuse segments would no longer be guaranteed. This is handled by a semiconductor switch which short-circuits the over-voltage immediately.

Abstract: A method and a circuit to achieve a low drop-out voltage regulator with a wide output load range has been achieved. A fast loop is introduced in the circuit. The circuit is internally compensated and uses a capacitor to ensure that the internal pole is more dominant than the output pole as in standard Miller compensation. The quiescent current is set being proportional to the output load current. No explicit low power drive stage is required. The whole output range is covered by one output drive stage. By that means the total consumption of quiescent or wasted current is reduced. An excellent PSRR is achieved due to load dependent bias current.

Abstract: A new battery charging, discharging, and protection circuit is achieved. The circuit comprises, first, a FET switch having gate, source, drain, and bulk. The FET switch may comprise either a NMOS device or a PMOS device. The source is coupled to a load terminal, and the drain is coupled to a battery terminal. Second, a means of controlling the FET switch gate and the bulk is included. The FET switch gate voltage determines the OFF and ON state of said FET switch. The bulk is switchably coupled between the battery terminal and the load terminal. A cascaded version is disclosed.

Abstract: A new current reference circuit is achieved. This current reference circuit is based on MOS transistors but does not depend upon the threshold voltage. The circuit comprises, first, a first MOS transistor having gate, drain, and source. A gate voltage value is coupled from the gate to the source. A second MOS transistor has gate, drain, and source. The second MOS transistor is of the same size and type as the first MOS transistor. The source is coupled to said first MOS transistor source. The gate voltage value plus a delta voltage value is coupled from the gate to the source. A means is provided for forcing a drain voltage value from the drain to the source of the first MOS transistor and from the drain to the source of the second MOS transistor. The first MOS transistor and the second MOS transistor conduct drain currents in the linear mode.