Abstract: A method and a circuit to monitor exactly the charge status of a battery of a battery powered device is achieved. The charge and discharge currents are continuously measured and integrated over time to get the exact charge of the battery. Inaccuracies caused by the offset of the integrators are precisely compensated by a bridge-like design of said circuit and by a feedback of said offset to the input of the integrators. The system is clocked in a way to enable a continuous operation. Another advantage is the low current consumption of the circuit by sharing some of the components for the integration of the currents and handling of the offset. The improved accuracy is optimizing the operation of said battery driven device and is avoiding any potential damage of the battery.

Abstract: A removable battery package incorporating electronic functions and a method to assemble said battery package is achieved. The battery package comprises one or more rigid or flexible battery cells of various shape and a smart card being wrapped around said battery cells to form an inside housing of the battery package casing. Said smart card could have customised dimensions to suit the battery cell and battery pack dimensions and could have the external connections on one side or on both sides. A cold welding process is possible to provide the connections from the battery tabs to said smart card.

Abstract: A new current reference circuit is achieved. This current reference circuit is based on MOS transistors but does not depend upon the threshold voltage. The circuit comprises, first, a first MOS transistor having gate, drain, and source. A gate voltage value is coupled from the gate to the source. A second MOS transistor has gate, drain, and source. The second MOS transistor is of the same size and type as the first MOS transistor. The source is coupled to said first MOS transistor source. The gate voltage value plus a delta voltage value is coupled from the gate to the source. A means is provided for forcing a drain voltage value from the drain to the source of the first MOS transistor and from the drain to the source of the second MOS transistor. The first MOS transistor and the second MOS transistor conduct drain currents in the linear mode.

Abstract: A circuit, where distortions, caused by PSRR in a mobile phone, are significantly reduced, is achieved. The power supplyvoltage for a signal processing module in a mobile phone is specially filtered by Low Drop Out (LDO) linear voltage regulators or other means of filtering. By filtering the noise in the power supply of a signal processing module the following output stage will not amplify the ripples caused by said noise. In a bridge configuration there is no more the requirement of a perfect symmetrical design and layout of the signal processing module, therefore the costs for manufacturing, design and layout are significantly reduced.

Abstract: A circuit, which is enabling the superpositioning of different audio signals such as voice, music or ringer signals in a audio output device is achieved. The individual superpositioning can be activated and performed by a combination of resistors and switches without the need of an additional mixing amplifier as in prior art. One common output stage is used for all the signals activated and superpositioned. The adjustment of the amplitude of the output signal, which can be used for the volume adjustment of a loudspeaker, is provided by a precise amplitude setting via the gain control stages of an inverting voltage amplifier through a current-voltage conversion. Said current-voltage conversion is performed by a string of resistors activated by a string of correspondent switches. This circuit reduces the power consumption, the chip area required and the offset and improves the power supply rejection rate (PSSR).

Abstract: A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.

Abstract: A method for tracking the MOS oxide thickness by the native threshold voltage of a “native” MOS transistor without channel implantation for the purpose of compensating MOS capacitance variations is achieved. The invention makes use of the fact that in MOS devices the threshold voltage is proportionally correlated to the oxide thickness of said MOS device. Said threshold voltage can therefore be used to build a reference voltage Vx+Vth which accurately tracks the MOS capacitance variations in integrated circuits. Circuits are achieved to create a frequency reference and a capacitance reference using said method. Additionally a method is introduced to create a capacitance reference in integrated circuits using said MOSFET capacitors.

Abstract: A circuit and a method for an effective way to customize the display driver software of any type of LCD-display and any type of LCD-driver chip used in an LCD display system is achieved. This is important in a multiple sourcing environment where LCD driver chips and LCD modules from different vendors are used in LCD display systems. This is accomplished through identification and registration of the information relevant for the said software customization by storing said information in an LCD module identification register. A microprocessor controlling the LCD display system is reading this identification register and providing the software customization elements specific to the LCD-driver chip and to the LCD-module during an initialization step of the system.

Abstract: A method and a circuit to monitor exactly the charge status of a battery of a battery powered device is achieved. The charge and discharge currents are continuously measured and integrated over time to get the exact charge of the battery. Inaccuracies caused by the offset of the integrators are precisely compensated by a bridge-like design of said circuit and by a feedback of said offset to the input of the integrators. The system is clocked in a way to enable a continuous operation. Another advantage is the low current consumption of the circuit by sharing some of the components for the integration of the currents and handling of the offset. The improved accuracy is optimizing the operation of said battery driven device and is avoiding any potential damage of the battery.

Abstract: Described is a low-dropout (LDO) voltage buffer implemented in CMOS with nearly rail-to-ail in/output operation which is capable of driving a large MOS gate. The voltage buffer utilizes a single mismatched input transistor pair with systematic offset which is biased to 350 mV below Vdd to operate at a reduced threshold voltage by utilizing the backgate effect (body effect). A dynamic biasing circuit is coupled to the input transistor pair to get high current efficiency. Reduced biasing to restore the full threshold voltage is achieved by shorting out resistive means coupled between the common bulk of the input transistor pair and the common bulk of the biasing circuit.

Abstract: An integrated circuit includes first circuit elements with a supply voltage which is equal to the external supply voltage of the IC, and second circuit elements with a supply voltage which is smaller than the external supply voltage and is derived as an internal supply voltage from the first supply voltage. An active voltage divider supplies the internal supply voltage and includes a first resistance voltage divider connected between the supply voltage terminal and the reference potential, an impedance transformer connected after the first resistance voltage divider, and a circuit for controlling the scaled voltage at the tap of the first resistance voltage divider as a function of the load of the second circuit elements.

Abstract: A regulated voltage supply circuit having improved power supply rejection ratio is achieved. The circuit comprises, first, a voltage follower having an input, an output, and a power supply voltage. The input is coupled to a reference voltage. The output comprises the regulated voltage supply. Second, a means of compensating noise on the power supply voltage comprises phase shifting the power supply voltage 180 degrees and feeding back the phase shifted power supply voltage to the voltage follower input to thereby improve power supply rejection ratio. The means of compensating noise may comprise an adjustable gain. This adjustable gain may further comprise an adjustable value resistance. The adjustable gain is used in a to optimize the PSRR by testing comprising modulating noise on the power supply voltage, measuring the noise on the regulated voltage supply, and adjusting the gain.

Abstract: A new battery charging, discharging, and protection circuit is achieved. The circuit comprises, first, a FET switch having gate, source, drain, and bulk. The FET switch may comprise either a NMOS device or a PMOS device. The source is coupled to a load terminal, and the drain is coupled to a battery terminal. Second, a means of controlling the FET switch gate and the bulk is included. The FET switch gate voltage determines the OFF and ON state of said FET switch. The bulk is switchably coupled between the battery terminal and the load terminal. A cascaded version is disclosed.

Abstract: In accordance with the objects of this invention, A battery protection circuit is achieved. The circuit comprises, first, a FET switch. Last, a control circuit determines the ON/OFF state of the FET switch. The FET switch and the control circuit comprise a single integrated circuit device. The control circuit may comprise over charge and over discharge detectors, a voltage reference, and a level shifter.

Abstract: A method to control the illumination intensity of a gas discharge lamp is achieved. The method comprises, first, converting an analog lamp illumination signal into a digital lamp illumination signal. The analog lamp illumination signal is a function of the illumination intensity of a gas discharge lamp. Second, digital target signal is subtracted from the digital lamp illumination signal to create a digital error signal. Third, a digital frequency set point is adjusted from a current value to a new value based on the digital error signal. The digital frequency set point is a high resolution digital value. Fourth, the current value and the new value are averaged by a digital delta sigma modulator to create a smoothed frequency set point. The smoothed frequency set point is a medium resolution value. Finally, an oscillating voltage signal is generated with a drive frequency based on the smoothed frequency set point. The drive frequency determines the illumination intensity of the gas discharge lamp.

Abstract: A new high voltage, high side driver circuit has been achieved. The circuit comprises, first, a top PFET having gate, drain, source, and bulk. The gate is coupled to a switching signal. The source is coupled to a high voltage. Second, a top resistor has first and second terminals. The first terminal is coupled to the high voltage. Third, a middle PFET cell comprises a middle PFET having gate, drain, source, and bulk. The source is coupled to the top PFET drain. The gate is coupled to the top resistor second terminal. A middle resistor has first and second terminals. The first terminal is coupled to the middle PFET gate. Finally, a middle means of claimping the middle PFET gate and a clamping voltage completes the middle PFET cell. Fourth, a bottom PFET cell comprises, first, a bottom PFET having gate, drain, source, and bulk. The gate is coupled to the middle resistor second terminal, the source is coupled to the middle PFET drain, and the drain forms a high side driver output.

Abstract: A circuit where the same amplifiers and the same volume adjustment circuitry are used for the ringer mode as well as for the audio mode of a mobile phone is achieved. The volume adjustment in the audio and ringer mode is provided by a precise amplitude setting via the gain control stages of an inverting voltage amplifier used in a bridge circuit through a current-voltage conversion. This volume adjustment circuit avoids the high power dissipation of a volume control through pulse width modulation (PWM) and avoids the risk of over-and undershooting of the amplifier's output signal due to a high slew rate in combination with the inductance of the loudspeaker. The current-voltage conversion is performed by a series of resistors activated by a series of correspondent switches. High impedance current less sense paths are eliminating the parasitic effect of the resistance of low cost standard switches to adjust the volume of the loudspeaker in the audio and the ringer mode.

Abstract: A charge/discharge protection circuit with n parallel load current switches and a control logic for the latter, which in an over-voltage event disconnects the battery from the charge/discharge terminals through sequentially controlled melting of integrated fusible links, can be placed on a smaller and therefore more economical chip, if the control logic (6) in an over-voltage event, simultaneously closes all load current switches (10 [1:n]), then following sequentially opens a first number of the load current switches, and at the same time closes the switch segment (12 [1:(m−1)]) of a short-circuit switch array associated with the respective load current switch, so that the former associated fusible links (11 [1:(m−1)]) melt sequentially; after the opening of this first number of load current switches the latter closes again and at the same time the remaining number (10 [m:n]) of still closed load current switches opens, as well as continues to sequentially

Abstract: A new current reference circuit is achieved. This current reference circuit is based on MOS transistors but does not depend upon the threshold voltage. The circuit comprises, first, a first MOS transistor having gate, drain, and source. A gate voltage value is coupled from the gate to the source. A second MOS transistor has gate, drain, and source. The second MOS transistor is of the same size and type as the first MOS transistor. The source is coupled to said first MOS transistor source. The gate voltage value plus a delta voltage value is coupled from the gate to the source. A means is provided for forcing a drain voltage value from the drain to the source of the first MOS transistor and from the drain to the source of the second MOS transistor. The first MOS transistor and the second MOS transistor conduct drain currents in the linear mode.

Abstract: A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.