Abstract: A system for accessing page table entries is disclosed. The system provides access to a page table entry mapping a predetermined physical page of memory. The system includes a physical page data base having an entry for each physical page of memory. Each physical page data base entry contains backlink information regarding an associated physical page of memory. The present system obtains a physical page data base entry associated with the predetermined physical page of memory from the physical page data base. The system uses a reserved page table entry, for example mapped by shared space, to build a virtual window. The virtual window provides a virtual address that may be used to access the page table entry mapping the predetermined physical page of memory. The virtual address provided by the virtual window is mapped to physical memory by the reserved page table entry.

Abstract: A virtual memory system is disclosed, providing a virtual address space of virtual addresses simultaneously available to a given process. The virtual address space includes a process private space accessible only to a given process, as well as a shared space of virtual addresses potentially accessible to two or more processes. The process private space includes virtual addresses on one side of a private/shared virtual address boundary, while the virtual addresses within the shared space are on the other side of the private/shared virtual address boundary. The private/shared boundary is ensured to be greater than a predetermined highest process private (or shared) virtual address of a different virtual memory system, and less than or equal to a predetermined lowest shared (or process private) virtual address of that different virtual memory system. Compatibility is ensured for software written for the different virtual memory system, allowing such software to run without modification on the present system.

Abstract: A technique for logically connecting local area networks (LANs) that may be separated by wide area networks containing routers and other network components. A logical link is formed between two bridge-like devices called tunnelers, such that, once a tunnel has been established between two LANs, other devices on the LANs can communicate as if the tunnel were a bridge. The tunneling mechanism of the invention requires that each LAN or extended LAN have only one active tunneler at any particular time, referred to as the designated tunneler, and each of the tunnelers is configured to have knowledge of the identities of the other tunnelers. A tunnel is established after a successful exchange of messages between two tunnelers, and then traffic may be forwarded through the tunnel in a transparent manner. The tunneling mechanism permits messages to be forwarded between LANs separated by a wide area network containing routers.

Abstract: A graphics system for storing and editing graphic images represented by digital data, includes a frame memory for storing pixel data representing graphic images including first and second graphic objects. The pixel data is stored at addresses, each being associated with one or more graphic fragment forming the first and second graphic objects. First and second addresses are respectively associated with those of the graphic fragments forming the first and second graphic objects. A memory controller controls writing and reading the pixel data to and from the frame memory. A fragment editor is provided to receive the pixel data read from the first address and modify the associated fragment with the received pixel data so as to form modified pixel data. An address detector detects the first address responsive to a request to read the pixel data from the first address and the second address responsive to a subsequent request to read pixel data from the second address.

Abstract: An anti-slamming latch is described for removably installing a module housing into a bay in a frame having a predetermined width. The module housing has a guide pin on a front portion thereof projecting from said housing. The latch apparatus comprises a latch body supported from the frame allowing straightforward removal and insertion of a rear portion of the module housing into said bay. The latch body has a first channel therein adapted to receive and engage the guide pin when the body is in a first position. This channel has a closed end engaging the pin to prevent insertion of said module housing past a predetermined intermediate position in the bay. The latch body has a second channel intersecting the first channel forming a rounded protuberance therebetween.The module may not be further inserted by pushing on the module.

Abstract: A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

Abstract: A system indexes Web pages of the Internet. The pages are stored in computers distributively connected to each other by a communications network. Each page has a unique URL (universal record locator). Some of the pages can include URL links to other pages. A communication interface connected to the Internet is used for fetching a batch of Web pages from the computers in accordance with the URLs and URL links. The URLs are determined by an automated Web browser connected to the communications interface. A parser sequentially partitions the batch of specified pages into indexable words where each word represents an indexable portion of information of a specific page, or the word represents an attribute of one or more portions of the specific page. The parser sequentially assigns locations to the words as they are parsed. The locations indicates the unique occurrences of the word in the Web. The output of the parser is stored in a memory as an index. The index includes one index entry for each unique word.

Abstract: An apparatus is provided for reducing read latency for an I/O device residing on a first bus having a first, short read latency timeout period. The apparatus includes a I/O bridge on a second bus having a second, longer read latency timeout compared to that of first bus which modifies read transactions into two separate transactions. A first transaction is a write transaction to the same address requested by the read transaction. This transaction forces a write-back if the address hits in a CPU's write-back cache. Thereafter the read transaction is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the first bus having a short read latency timeout period from exceeding it's read latency timeout limit.

Abstract: A memory of a computer system is sized and configured after the memory has been loaded with data. The sizing and configuration of the memory causes the data to become scattered among memory chips on a single memory module or among two or more memory modules. To gather the data, gather code loads itself into the instruction cache of the computer system and while executing from the instruction cache configures the memory and gathers the data in the memory such that it is again located at the same address it held before the configuration occurred.

Abstract: A composite shelf in a shelf frame supports a plurality of disk drives and attenuates vibrations in the shelf. In the composite shelf, there is a double wall having an outer wall and an inner wall for supporting the disk drives mounted on the shelf. A stiffener between the inner wall and outer wall strengthens the composite shelf to reduce flexure in the composite shelf when the shelf is loaded by disk drives mounted on the shelf. A damping layer is placed between the stiffener and one of the inner wall or outer wall. This damping layer attenuates vibrations in the composite shelf so as to reduce vibrations transmitted from the composite shelf to the disk drives supported by the composite shelf. A second damping layer is placed between the stiffener and the other wall. Both damping layers attenuate vibrations in the composite shelf so as to reduce vibrations transmitted from the composite shelf to the disk drives supported by the composite shelf. A third damping layer may be placed within the stiffener.

Abstract: A boot strap assignment system is disclosed for a symmetric multiprocessor computer in which the role of the boot strap processor is assigned to one of the working processors by a central agent as part of power-on configuration. The system includes a system management processor which monitors the operation of the multiprocessor computer and controls a switching circuit that selectively transmits the boot strap assignment signal from the central agent to the working processors. Since the management processor monitors environmental conditions and shut-down events, it can predict the failure of working processors and assign the bootstrapping function appropriately. A watch dog timer is also provided in case the bootstrapping fails so that another working processor can be assigned the task of booting up the computer.

Abstract: A computer enclosure has a front bezel with two doors and a two-way lock mechanism controlling the locking of the doors. The swinging ends of the doors meet at a central portion of the bezel where the lock mechanism is located. The lock mechanism includes a guide plate located at the rear of the bezel having two guide channels that receive the bolts of the lock mechanism. A lock extends through the guide plate, and its rotatable barrel attaches to a cam plate at the rear of the bezel. The cam plate has two slots, each engaging one of the bolts. The bolts slide between withdrawn and extended positions in response to urging forces from the edges of the slots as the cam plate rotates in response to the turning of the lock, thus locking and unlocking the doors.

Abstract: In a computerized method, performance data collected while a computer system executed instructions of a program are analyzed. The method collects performance data while executing the program. The performance data includes sample counts of instructions executed. The program is analyzed to determine classes of instructions. Instructions of the same equivalence class all execute the identical number of times. The execution frequencies for each instructions of each equivalence class is estimated. The estimated execution frequencies can then be used to determine the average number of cycles required to issue each instruction of each equivalence class. The average number of cycles can be compared with the minimum number of cycles to determine the number of dynamic stall cycles incurred by the instructions. Furthermore, reasons for the dynamic stall cycles can be inferred.

Abstract: A database co-processor for efficient sequential data retrieval from a relational database is provided which is adapted for connection to a host system via a two-way bus. The database co-processor includes an interface unit connected to receive and transmit data over the two-way bus and a database engine connected to the interface unit by input and output bus means. The database engine includes a relevant field selection unit for storing selection criteria relevant to a database query raised by the processor. A comparator which is incorporated into the database engine compares input candidate data received on the input bus in accordance with the selection criteria and produces a result. The database engine further includes a storage medium for the storage of output candidate data received on the input bus.

Abstract: A computer method and apparatus determines keywords of documents. An initial document by term matrix is formed, each document being represented by a respective M dimensional vector, where M represents the number of terms or words in a predetermined domain of documents. The dimensionality of the initial matrix is reduced to form resultant vectors of the documents. The resultant vectors are then clustered such that correlated documents are grouped into respective clusters. For each cluster, the terms having greatest impact on the documents in that cluster are identified. The identified terms represent key words of each document in that cluster. Further, the identified terms form a cluster summary indicative of the documents in that cluster.

Abstract: A speed and memory control system and method for use with a sort accelerator having a rebound sorter and merger is disclosed. The speed and memory control system includes a variable length shift register which utilizes circulating RAM indexing, tag extraction lookahead features to speed up access of records, and merge lookahead and memory management features to provide quick and effective storage of records.

Abstract: A computerized method optimizes an index of information stored as records of a database in response to queries made to the index. The index is generated by storing index entries in a memory. Each index entry includes a word entry immediately followed by one or more location entries. The word entry encodes a unique portion of information of the records, and the location entries encode occurrences of the unique portion of information in the records. A query phrase is processed, the phrase corresponds to a concatenation of adjacent portions of indexed information. A measure of the amount of time required to process the phrase is recorded in a journal. Periodically, the journal is processed and new index entries are generated for the phrases if the processing of the phrase exceeds some predetermined threshold time.

Abstract: In accordance with the present invention, an apparatus includes a system bus having memory bank identification signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank, and at least one commander module. The commander module contains decode logic which includes memory mapping registers associated with unique values to be driven on the memory bank identification signals. The memory banks contain compare logic including a virtual node identification register which stores a predetermined value to be compared with the value driven on the memory bank identification signals to determine if the memory bank is the target of the current transaction. Thus, memory banks need not decode the entire system bus address to determine if they are the target of the transaction which reduces the time required to complete a transaction with memory.

Abstract: A driver circuit for limiting electrical noise on a quiescent signal is provided which includes a Transition High Driver circuit, a Transition Low Driver circuit, a Quiescent High Driver circuit, and a Quiescent Low Driver circuit. The driver circuit comprises means for driving an electrical signal with a presumed noisy Transition Power Supply network while it is transitioning from a low voltage level to a high voltage level or vice versa. The signal is driven by the Transition Power Supply network until the electrical signal reaches its quiescent voltage level. At this time, the signal is no longer driven by the Transition Power Supply network but rather by a presumed clean Quiescent Power Supply network. In this manner, noise from transitioning signals is prevented from coupling onto quiescent signals.