Abstract: A system for locating stored information using an index includes a memory and processor. The memory stores an index which includes a plurality of index entries. Each of the index entries corresponds to a respective one of a plurality of terms associated with the stored information and has one or more location identifiers. Each of the location identifiers represents a location within the information at which the corresponding term is associated with the information. The processor searches the stored index to identify the location identifiers of at least two index entries which correspond to terms of interest. The processor also determines the locations within the information which are represented by the identified location identifiers and at which the terms of interest have a relationship as indicated by a particular operator (e.g. "and").

Abstract: A method is provided for optimizing a program by inserting memory prefetch operations in the program executing in a computer system. The computer system includes a processor and a memory. Latencies of instructions of the program are measured by hardware while the instructions are processed by a pipeline of the processor. Memory prefetch instructions are automatically inserted in the program based on the measured latencies to optimize execution of the program. The latencies measure the time from when a load instructions issues a request for data to the memory until the data are available in the processor. A program optimizer uses the measured latencies to estimate the number of cycles that elapse before data of a memory operation are available.

Abstract: In a computer implemented method, a plurality of records are stored in a database at unique record addresses. The information of each record is parsed into a set of individual words where each word represents a portion of the information of a particular record. A unique sequential location is assigned to each word so that the location of a first word of a next record sequentially follows the location of a last word of a previous record. Pairs are formed from the words and their assigned location. For attributes common to a particular record, generate a record metaword, and assign the location of the last word of the record to the metaword. For attributes common to subsets of words, generate a first and second field metaword, and assign the location of the first and last word of the subset to the first and second field metaword to form pairs.

Abstract: In a modular tower building block system for containing computing system devices, a power bus is incorporated into the modular blocks of the building block system by using a printed circuit board to carry the power bus in each modular block. The printed circuit board is mounted and positioned in each modular block to electrically connect with a printed circuit board in a next adjacent modular block when two modular blocks are stacked on each other. Also, there are a plurality of three-phase power buses on the printed circuit boards and only one phase of each power bus is distributed from each modular block. The printed circuit board is precisely located in each modular block at a predetermined position. Alignment pins and receivers provide alignment between stacked modular blocks to precisely position one modular block to the other modular block.

Abstract: A method for mapping a plurality of index entries in an index of a database includes parsing one or more records into elements, allocating each of the elements to one of a plurality of element groupings, and storing a representation of each of the elements in an index in conjunction with representations of other of the elements within its element grouping.

Abstract: In a computer implemented method, instructions of a program are mapped into a cache memory of a computer system. The cache memory is partitioned into a plurality fixed size lines for the convenience of accessing the instructions. Each block is assigned a different identification, for example a unique color. The program is partitioned into a plurality of instruction units, for example procedures or basic blocks. A flow graph is generated for the program. In the graph, nodes represent the instructions units, and edges directly connect nodes that have an execution relationship. Instruction units of directly connected nodes are mapped into blocks having different identifications or colors. An unavailable-set of identifications is maintained for each node.

Abstract: A network device for interconnecting computer networks, the device including a bridge having a plurality of ports through which network communications pass to and from the bridge, the bridge also including a first interface enabling a user to partition the plurality of bridge ports into a plurality of groups, wherein each group represents a different virtual network, wherein the bridge treats all ports within a given group as part of the virtual network corresponding to that group and the bridge isolates said virtual networks from each other, whereby any communications received at a first port of the bridge are directly sent by the bridge to another bridge port only if the other bridge port and the first bridge port are part of the same group.

Abstract: A program for monitoring computer system performance includes a collection of source code modules in the form of a high level language. Each of the source code modules is compiled into a corresponding object code module. The object code modules are assembled into machine dependent code. The machine code is translated into a program module in the form of a machine independent register translation language. The program module is partitioned into basic program components. The basic program components include procedures, basic blocks within procedures, and instructions within basic blocks. Fundamental instrumentation routines identify, locate, and modify specific program components to be monitored. The modified basic program components are converted to an instrumented machine executable code to be executed in the computer system so that performance data can be collected while the program is executing in the computer.

Abstract: A document condensation method and apparatus produce a document synopsis are provided in which automatic indexing techniques are used to analyze an input document to determine a list of words and phrases characteristic of the subject matter of the document. Sections of the document are compared to the list of characteristic words and phrases to determine which sections of the document are most like the overall document in view of subject matter. A predetermined number of sections determined to be most similar to the overall document in content are provided as a condensed version of the whole document.

Abstract: A small bimetallic thermocouple probe device for use in scanning atomic force microscopy is mass produced by etching and oxidatively sharpening silicon points on a standard silicon wafer. The sharpened points are oxidized and the first thermocouple metal layer is deposited and patterned. The intermetal dielectric layer is deposited and removed in the area of the tip of the probe by a simple double spin photoresist process having a drying cycle between the two spins. The exposed tips have the dielectric etched, and the second thermocouple metal is deposited and patterned. The finished thermocouples are produced by etching the silicon from the back side of the wafer to free up the cantilevered structure which the probe are constructed upon. With such a procedure, large numbers of tiny, low thermal mass scanning atomic force microscope thermocouple probes may be inexpensively manufactured.

Abstract: The invention is a system providing adaptive stream buffers using instruction-specific prefetching avoidance (ISPA). According to the invention, each time the CPU executes an instruction resulting in prefetched cache lines not being used, the instruction address is stored in a table. Subsequent instruction addresses are compared to the instruction addresses in the table, and a stream buffer is not allocated when the subsequent instruction address is found within the table.

Abstract: A method and apparatus for transferring data units between a host memory and a peripheral interface, the data units being subject to a flow control mechanism whereby some of said data units are flow controlled and some of said data units are not. Two transmit buffer memories are coupled to the peripheral interface; one for storing controlled data units to be transferred to the peripheral interface and the other for storing uncontrolled data units to be transferred to the peripheral interface. A single request buffer stores successive requests for data to be transferred from a host memory to either of the two transmit buffer memories. Data transfer circuitry transfers data from the host memory to either of the two transmit buffer memories in response to the requests stored in the request buffer.

Abstract: A method for generating test cases for testing integrated circuits which comprises the step of apportioning a plurality of instructions into a plurality of groups of test instructions. At least some of the plurality of groups include a plurality of control flow instructions each of which transfer execution to a different one of the plurality of groups. This method prevents a test of an integrated circuit from entering an infinite loop.

Abstract: A system and method for automatically mapping on a computer display a graphical representation of a physical arrangement of a plurality of computer components in one or more cabinets, each cabinet having one or more shelves for housing the computer components. The status of the components is periodically monitored and the computer display updated accordingly. A graphical user interface is provided for user observation of the physical arrangement and status of computer components in the cabinets, as well as user control of the operational parameters of the components.

Abstract: An adjustable filter for a computing system having memory error detecting and correcting features selectively masks user-specified errors, thereby preventing storage of such errors in a control and status register (CSR). The invention includes a command and data register 102; a CSR 103; an error detecting and correcting circuit 108, including a check bit generator 108a, an error detecting circuit 108b, and an error correcting circuit 108c; a memory module 114; and filter logic 300. The contents of a filter control register 220 of the CSR 103 operate to specify a particular error which is to be "filtered". The filter logic 300 includes a plurality of logic gates that compare the user-specified signals stored in the register 220 with error-related signals reported by the error detecting circuit 108b. If the signals match, information associated with the detected error is prevented from being stored in the CSR 103.

Abstract: A method and apparatus for monitoring a physical process comprising a plurality of interacting attributes where the attributes are components of the physical process. The method and apparatus locates defective attributes and defective interactions between interacting attributes within the physical process. The apparatus comprises a processor, and input member and a hierarchical data structure. Data concerning the attributes of the physical process are input and organized into the hierarchical data structure. A response variable and a variation in the response variable for each population in the hierarchical data structure is determined, and used to identify defects in the physical process.

Abstract: In a distributed network, client computers are connected to server computers. The server computers store a plurality of Web pages. The Web pages are partitioned into sets, where each set includes Web pages that are substantially similar in content. A preset compression dictionary is generated for each set of Web pages. In addition, a fingerprint is generated for each preset dictionary. The fingerprints uniquely identify each of the preset dictionaries. When one of the client computers requests one of the Web pages, a compressed form of the Web page is sent along with the fingerprint of the dictionary that was used to compress the Web page. The client computer can then request the preset dictionary in order to decompress the Web page when the client does not have a copy of the preset dictionary.

Abstract: A prediction mechanism for improving direct-mapped cache performance is shown to include a direct-mapped cache, partitioned into a plurality of pseudo-banks. Prediction means are employed to provide a prediction index which is appended to the cache index to provide the entire address for addressing the direct mapped cache. One embodiment of the prediction means includes a prediction cache which is advantageously larger than the pseudo-banks of the direct-mapped cache and is used to store the prediction index for each cache location. A second embodiment includes a plurality of partial tag stores, each including a predetermined number of tag bits for the data in each bank. A comparison of the tags generates a match in one of the plurality of tag stores, and is used in turn to generate a prediction index.

Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Abstract: In order to provide a thermal coupling between a heat source and a heat sink, an integrated interleaved-fin connector is provided. A first substrate includes a first side surface and a second side surface. A plurality of heat generating devices are formed in the first side surface. A plurality of first channels are etched in the second side surface to form a plurality of first fins. A second substrate has a plurality of second channels etched therein to form a plurality of second fins and a base. The base is for thermally engaging with a heat sink. The first and second fins providing a thermally conductive path from the heat generating devices to the heat sink when interleaved with each other.