Abstract: An architecture, module set and platform to provide total power protection from utility disturbances. Power supplies employing the invention are built on power buses for utility AC input, battery DC input and conditioned AC output housed in the platform and employ modular line-to-AC-or-DC power-factor-correcting converters and battery/charger sets either housed in the platform or integrated as part of the front end power supply for a critical load such as a computer.

Abstract: Racks of modules especially useful for retaining disk drives, tape drives, controllers, computers and the like are fabricated via use of tower building blocks. Each block contains a latch arrangement for securing it to another block, a base unit or a cap unit with the latch effecting interlocking of the blocks so as to form a sturdy assembled structure. Power and/or electrical communication lines are provided in each block with power passing through one vertical array of blocks and electrical communications passing through the other so as to reduce the need for shielding one from the other. An arrangement of alignment pins and mating receptacle holes in conjunction with selected placement of sliding latch elements can facilitate proper coupling of blocks which have similar electrical path boards therein.

Abstract: Local clock data is collected at run time in a multiprocessor system. Postprocessing is used to determine a global time base from the local clock readings. Clock drift and offset parameters are calculated for the local clocks. These parameters are used to adjust the time stamps of events in a global event log in order to create a global time base. A first method is used to calculate clock drift and offset parameters between processors with too or more event pairs oriented in the same direction. A second method is used to calculate clock drift and offset parameters between processors with event pairs oriented in opposite directions. A third method is used where the processors have no event pairs between them.

Abstract: In a multiblower system for cooling electronic components, each blower has a backflow preventor. The backflow preventor has two pieces of flexible material and a screen attached to the intake side of the blower assembly. Each of the pieces of flexible material is scored through to form a petaled opening through which air may pass. The scores on one of the pieces of flexible material are out of alignment with the scores on the other piece when assembled together in the blower assembly. When the blower is running, the petals in the pieces of flexible material open to allow air to pass through the blower assembly. When the blower is stopped, the petals are closed against the screen due to the pressure differential between the inside of the enclosure and the outside of the enclosure caused by the effect of the draw of the other blowers in the system.

Abstract: A system and method for determining the physical presence, proper electrical coupling and predetermined identifying characteristics and attributes of various computer system elements and components, including both fixed and removable modules such as field replaceable units ("FRUs"), utilizing a minimum number of signal lines per component. In a preferred embodiment, a voltage divider is established between a first resistance in an environmental monitoring unit ("EMU") and a second resistance in an associated FRU wherein a voltage level taken intermediate the first and second resistances is indicative of a particular FRU attribute.

Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.

Abstract: A memory controller such as for use with a synchronous dynamic random access memory (SDRAM) wherein an active row at the end of each transfer can either be left active or closed by precharging the row. The memory controller uses a history register to keep track of the results of a number of prior accesses to each memory bank, remembering whether the access was to the same row as an immediately prior access. For each new memory access, the memory controller either asserts or deasserts a precharge enable signal depending on the state of the history bits. As a result, the memory controller is more likely to have a correct row open on a subsequent access, and less likely to have a wrong row open.

Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

Abstract: A method of accessing a content addressable memory storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state, is disclosed. The stored information is compared with a one bit signal. A match is indicated when the one bit signal represents a logic zero and the stored information represents the don't care state, or when the one bit signal represents a logic one and the stored information represents a don't care state. An absence of a match is indicated when the one bit signal represents a logic zero and the stored information represents an invalid state, or when the one bit signal represents a logic one and the stored information represents the invalid state. The content addressable memory is especially adapted for use in a translation buffer providing variable page granularity. The don't care state permits multiple virtual page numbers to match a single entry storing information for multiple physical pages.

Abstract: A method and apparatus for controlling the providing of conditioned AC power, with the conditioned AC power being capable of being provided on a continuous basis. Unconditioned AC voltage is received by transverters. The transverters convert the unconditioned AC voltage into a transverter AC output voltage. The transverter AC output voltage is monitored by current and voltage sensors. A transverter control signal is developed in response to changes in the current and voltage sensing in comparison with a reference signal. The transverter control signal then regulates conversion of the transverter AC output voltage into the desired conditioned AC output voltage. In multi-phase AC voltage systems conditioned AC voltages for each phase are provided.

Abstract: A computer implemented method for dynamically setting hint fields of instructions. Machine executable code is modified during execution to locate and replace instructions having hint fields. The instructions are replaced with calls to intercept the execution flow and redirect to procedures of a monitor. During execution of the machine executable code, hint information is recorded in a memory. The recorded hint state information is analyzed to determine the most frequently occurring or best hint value. When a best hint value has been determined, the replaced instructions are restored with best hint values.

Abstract: An electrostatic discharge protection system provides electrostatic discharge protection for an integrated circuit having a package and a semiconductor device installed within the package. The package includes a first pin, a second pin and a reference pin. The semiconductor device includes a first conductor that connects with the first pin, a second conductor that connects with the second pin, and a reference conductor that connects with the reference pin. The integrated circuit operates within one of a normal operating mode and a power conservation mode when the first and second pins receive a power supply signal. The electrostatic discharge protection system includes a first protection device that detects and couples electrostatic discharge events from the first conductor to the reference conductor by reference to a voltage potential difference between the second conductor and the reference conductor.

Abstract: Semiconductor package and method in which a chip is mounted in an opening in a frame with the back side of the chip facing outside the package, and a heatsink is positioned in direct thermal contact with the back side of the chip. In one preferred method of manufacture, the chip is mounted in the frame and tested before the heatsink is attached.

Abstract: In a computer implemented method, possible arrangements of items, such as components to be placed on a semiconductor die, are described in a permutation space expressed as a data structure stored in a memory. The data structure is in the form of a balanced tree. In the tree, each node is a possible permutation. The ordering in the permutation space is transformed to an ordering described in a vector space using an inversion table. A best ordering of items is determined in the vector space according to a predetermined criterion such as an objective function. The best ordering as determined in vector space is then transformed back to the permutation space to determine an optimal placement of the item according to the predetermined criterion.

Abstract: In a computerized method, speech signals are analyzed using statistical trajectory modeling to produce time aligned acoustic-phonetic units. There is one acoustic-phonetic unit for each portion of the speech signal determined to be phonetically distinct. The acoustic-phonetic units are translated to corresponding time aligned image units representative of the acoustic-phonetic units. An image including the time aligned image units is displayed. The display of the time aligned image units is synchronized to a replaying of the digitized natural speech signal.

Abstract: A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.

Abstract: In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further that notification of non-error and maintenance status changes are processed with minimal latency.

Abstract: A method and apparatus for generating test data is presented. A data generator produces data using element specifications contained in an input script. The data generator includes a specification analyzer and data synthesizer. The data generator produces the data that includes varied combinations of the element specification generated in a particular order. Both the combination and the particular order in the generated sequence may vary in accordance with a specified method of data generation. Three methods of data generation--carry-out method, grey code method, and all-change method--are described.

Abstract: A circuit for limiting voltage transient excursions on a power supply node is disclosed. The circuit includes a first field effect transistor dispose to provide a capacitance and having source and drain electrodes coupled to said external supply node path and having a gate electrode and first and second clamp transistors. A resistance is coupled between the gate electrode of said first transistor and the internal supply return node and to gate electrodes of the clamp transistors. The circuit also include process resistances between internal and external supply connection to provide a charge transfer path between external and internal supply nodes and external and internal return nodes.

Abstract: A packaging system for use with irregular shaped articles is described. The system includes a carton having slotted sidewall members disposed to receive suspension folders at least one suspension folder. The suspension folder includes a layer of a packaging material having a pair of apertures and having a pair of creases disposed along a region of the layer coextensive with an edge portion of each one of the apertures. The layer is provided with a stretchable material bonded to a first surface of said layer of packaging material. A strong hinge is provided at portions of the layer disposed along the edges of the pair of apertures to join the first and second portions of the layer of packaging material.