Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A variable wavelength transceiver includes a first variable wavelength transmitter, capable of generating an electromagnetic wave of a first wavelength, a second detector of an electromagnetic wave of a second wavelength, and a collision detector coupled to the second detector and the variable wavelength transmitter, the collision detector determining when the energy level of the second detector exceeds a threshold value while the variable wavelength transmitter transmits the electromagnetic wave.

Abstract: A method of operating a multiprocessor system having a predefined number of processing units for processing data, includes obtaining load information representing a loading of each of a number of randomly selected ones of the processing units. The number of randomly selected processing units is greater than 1 and substantially less than the predefined number of processing units. A least loaded of the randomly selected processing units is identified from the obtained load information. The data is directed to the identified least loaded randomly selected processing unit for processing.

Abstract: A local client computer includes a local hypertext server, a local application program, and a downloader for downloading a copy of a remote network document (local copy), that is accessible by the local application program, onto the client computer. When connected to the network, a downloader is executed to create the local copy on the client. When disconnected, the local copy may be accessed and modified through the client browser in a manner that is similar to when the client is connected to the network.

Abstract: A new method of fabricating a new vertical bipolar transistor in a protection circuit is disclosed. In the disclosed system, a layer of gate electrode material is formed over a selected surface of a silicon wafer. The gate electrode material is patterned to form gates between an emitter stripe and a base contact within the bipolar transistor. In an example embodiment, the gate as well as the emitter stripe are coupled with an input source such that excess voltage is limited and excess current sunk during ESD events on the input source. A conductive channel under the gate is formed in the presence of an ESD event on the input source. The channel conductance may further be enhanced by introduction of an appropriate dopant material. Sidewall spacers may be formed adjacent to the base/emitter isolation regions. Where the bipolar transistor is a PNP transistor, a light dosage of an n-type dopant may be implanted into the base contact prior to forming the sidewall spacers.

Abstract: A SCSI bus extender apparatus coupling a primary SCSI bus to a secondary SCSI bus includes a mechanism for detecting and resolving contention between a substantially simultaneous SELECTION operation on the primary bus and a RESELECTION operation on the secondary bus. The inventive method contemplates the bus extender arbitrating for control of the primary bus after a conflict is detected, and releasing control of the secondary bus if control of the primary bus is obtained. A target device on the secondary bus can then rearbitrate for control of the secondary bus. Once the target device controls the secondary bus, it can direct a RESELECTION signal to the bus extender, which responsively directs the signal to an initiator device on the primary bus. If the bus extender is unable to gain control of the primary bus after a conflict is detected, the SELECTION operation is allowed to proceed and the target device reattempts to assert the RESELECTION operation thereafter.

Abstract: A computer system includes a plurality of processor modules coupled to a system bus with each of said processor modules including a processor interfaced to the system bus. The processor module has a backup cache memory and tag store. An index bus is coupled between the processor and the backup cache and backup cache tag store with said bus carrying only an index portion of a memory address to said backup cache and said tag store. A duplicate tag store is coupled to an interface with the duplicate tag memory including means for storing duplicate tag addresses and duplicate tag valid, shared and dirty bits. The duplicate tag store and the separate index bus provide higher performance from the processor by minimizing external interrupts to the processor to check on cache status and also allows other processors access to the processor's duplicate tag while the processor is processing other transactions.

Abstract: A circuit for limiting voltage transient excursions on a power supply node is disclosed. The circuit includes a first field effect transistor dispose to provide a capacitance and having source and drain electrodes coupled to said external supply node path and having a gate electrode and first and second clamp transistors. A resistance is coupled between the gate electrode of said first transistor and the internal supply return node and to gate electrodes of the clamp transistors. The circuit also include process resistances between internal and external supply connection to provide a charge transfer path between external and internal supply nodes and external and internal return nodes.

Abstract: A method and an apparatus analyze a computer program for dependencies of the program output on the program input. To analyze the program, the program is transformed by a function into a Boolean expression called a verification condition. An example of this function is the weakest liberal precondition. The verification condition characterizes a condition between the input and the output of the program that must be satisfied for the output to be independent of the input. A theorem prover evaluates the verification condition to determine whether the output would depend on the input if the program was executed. If the verification condition evaluates to true, then the output is independent of the input; false, then the output depends on the input.

Abstract: A new virtual memory system is disclosed having a virtual address space including a gap of inaccessible virtual addresses within the virtual address space. A new virtual memory allocation routine is disclosed providing a starting address of accessible virtual addresses allocated to a currently executing process in a response to a request. The accessible virtual addresses are virtually contiguous, and include no addresses from within the gap of inaccessible virtual addresses. A new virtual memory deallocation routine is further disclosed providing deallocation of ranges of virtual addresses which may or may not include addresses within the inaccessible gap.

Abstract: A locking member formed of resilient material for locking a disk drive within a computer enclosure includes a first cantilevered beam portion positioned along a first side of the disk drive. A first locking protrusion is positioned on the first cantilevered beam portion and is capable of engaging with the enclosure for locking the disk drive therein. A handle portion extends from the cantilevered beam portion for resiliently bending the first cantilevered beam portion inwardly to disengage the first locking protrusion from the enclosure.

Abstract: A method for use in the design or implementation of a synchronous circuit having nodes interconnecting logic functions and in which the nodes assume logic values in successive clocked phases of a logical cycle. For a phase for a node connected to an output of a logic function, a determination is made (and stored) of which nodes, connected to inputs of the logic function, have and do not have timing behaviors in that phase which are needed in order to determine the logic value assumed by the output node in that phase.

Abstract: Apparatus for communication in a fiberoptic LAN includes a first transmitter of an electromagnetic wave of a first wavelength, a second detector of an electromagnetic wave of a second wavelength, and an optical coupler coupled to the first transmitter, the second detector, and the fiberoptic LAN.

Abstract: A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.

Abstract: Strings, such as Web pages or other documents, are fingerprinted in order to detect substantially similar strings, so as to avoid processing duplicate strings. At the same time determine a computerized method estimates the probability that a collision among fingerprints of dissimilar strings. As fingerprints are generated for strings presented for processing, when the fingerprint of a string is determined not to be identical to any fingerprint in a set of stored fingerprints, the new fingerprint is masked and the unmasked portion of the fingerprint is compared with a corresponding portion of the fingerprints in the stored set. Information is recorded regarding the number of matching masked fingerprints.

Abstract: A Web crawler system and method for quickly fetching and analyzing Web pages on the World Wide Web includes a hash table stored in random access memory (RAM) and a sequential Web information disk file. For every Web page known to the system, the Web crawler system stores an entry in the sequential disk file as well as a smaller entry in the hash table. The hash table entry includes a fingerprint value, a fetched flag that is set true only if the corresponding Web page has been successfully fetched, and a file location indicator that indicates where the corresponding entry is stored in the sequential disk file. Each sequential disk file entry includes the URL of a corresponding Web page, plus fetch status information concerning that Web page. All accesses to the Web information disk file are made sequentially via an input buffer such that a large number of entries from the sequential disk file are moved into the input buffer as single I/O operation.

Abstract: A computer implemented method indexes duplicate information stored in records having different unique addresses in a database. A fingerprint is generated for each record, the fingerprint is a singular value derived from all of the information of the record. The fingerprint is stored in the index as a unique fingerprint if the fingerprint is different than a previously stored fingerprint of the index. A reference to the unique address of the record is stored with the fingerprint. If the fingerprint is identical to the previously stored fingerprint, then store the reference to the address of the record with the previously stored fingerprint.

Abstract: A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.

Abstract: A new system and method for outswapping a process is disclosed. The new system forms one or more working set list chains (also referred to as "page table chains") during the outswap process. The new system then conveniently locates and outswaps a number of page table pages of the process to be outswapped by traversing the working set list chains. In a preferred embodiment, the forming of each working set list chain is performed while traversing a working set list during outswapping of a number of body pages of a process. Each working set list entry potentially describes a page of virtual memory in use by the process to be outswapped. In a further aspect of the disclosed system, traversing the working set list of the process to be outswapped includes determining whether each one of the working set list entries indicates a private page table page. If an entry in the working set list indicates a private page table page, the present system adds a link to a working set list chain.

Abstract: A computer system is directed to convert a program written as a plurality of high level source code modules into corresponding machine executable code. The source code modules are compiled into an object code module, and the object code modules are translated into a single linked code module in the form of a register translation language and logical symbol table compatible with a plurality of computer system hardware architectures. The source code program structures are recovered from the linked code module, and the linked code module is partitioned into a plurality of procedure, and instructions of each of the procedures grouped into basic blocks. A procedure flow graph is constructed for each of the procedures, and a program call graph is constructed for the linked code module. The linked code module is modified by eliminating dead code and moving loop-invariant code from loops.