Abstract: A compiler-loader system enables the creation of different loaded executable images in target computers complying with different versions of an instruction-set architecture, the different images being created from a single executable program on secondary storage. The compiler generates an executable program containing a routine executable on both versions of the target computers, and also containing an architecture entry with (i) an address of the program location from which the routine is called, (ii) an instruction executable on only one version of the target computers that performs the same function as the routine but with superior performance, and (iii) a value indicating which version of the target machines the instruction can be executed on. The loader determines whether the target machine can execute the instruction, and if so replaces the subroutine call appearing at the address in the architecture entry with the instruction appearing in the architecture entry.

Abstract: A time-based and event-based interrupt frequency mitigation scheme is provided. A holdoff event counter is programmed to count a holdoff event count corresponding to a number of interrupts. A holdoff timer is programmed to time a holdoff interval representing the time period to elapse before the generation of an interrupt request to the host system can occur. When a data transfer request associated with the transfer of data from or to the host system is serviced and results in the occurrence of an interrupt event, the holdoff event counter is modified by one. If either the holdoff event counter or the holdoff timer has expired and the interrupt is enabled, an interrupt request to the host system is generated. In response to such interrupt request generation, the interrupt is processed and both the holdoff event counter and the holdoff timer retriggered.

Abstract: The invention includes an apparatus and method for buffering data transmitted by a processor and received by an I/O device via a memory and buses. The memory arranged at a plurality of levels includes a lower level of the memory operating faster than a higher level of the memory. A plurality of ring buffers are allocated at different levels of the memory and available buffers at a lowest possible level of the memory are preferentially selected as write buffers to store data transmitted by the processor. The apparatus includes a first level of the memory arranged on an integrated circuit with the processor, a second level of the memory arranged in an off-chip cache, and a third level of the memory arranged in a dynamic random access memory. Read buffers are selected to store data to be received by the I/O device. Stored control values indicate the order for selecting the read buffers and are used by the processor to select the write buffer.

Abstract: An apparatus and method for counting event signals generated by a computer system is described. The event signals are indicative of the performance of the computer system. Programmable logic enhances the functionality of performance counters by enabling the system user to specify, during the execution of an application program, which event signals to count. The system user can dynamically configure the programmable logic to select a subset of the event signals generated by the computer system, and to combine the selected subset of event signals to generate a new event signal that can be counted. Other new event signals can be generated by the programmable logic from the selected subset of event signals. A user of the computer system can dynamically make the selection of any one of the new event signals for counting.

Abstract: A processor includes an execution pipeline and a retire unit coupled to an end of the execution pipeline. The processor executes instructions of a program. An apparatus for collecting performance data while the instructions are executing includes a register coupled to the retire unit of the processor. Means are provided for incrementing the register whenever an instruction is retired from the execution pipeline. In addition, the apparatus includes means for generating an interrupt to an interrupt handler whenever the register is incremented to a predetermined value.

Abstract: In a relaxed bus protocol for transferring bursts of data from a slow device to another device, a predictor generates an advance signal. The advance signal is used to load next data into an output register of the slow device, the next data can then be transferred to the other device. A validator/corrector receiving a ready signal from the second device, the validator/corrector determines that the advance signal is correctly generated by the predictor. Heuristics and a higher level protocol adjust the size and frequency of the bursts of data to achieve optimal performance, and maintain correctness of transmitted data.

Abstract: A method of scheduling program instructions for execution in a computer processor comprises fetching and holding instructions from an instruction memory and executing the fetched instructions out of program order. When load/store order violations are detected, the effects of the load operation and its dependent instructions are erased and they are re-executed. The load is associated with all stores on whose data the load depends. This collection of stores is called a store set. On a subsequent issuance of the load, its execution is delayed until any store in the load's store set has issued. Two loads may share a store set, and separate store sets are merged when a load from one store set is found to depend on a store from another store set. A preferred embodiment employs two tables. The first is a store set ID table (SSIT) which is indexed by part of, or a hash of, an instruction PC.

Abstract: A computer implemented method performs constrained searching of an index of a database. The information of the database is stored as a plurality of records. A unique location is assigned to each indexable portion of information of the database. Index entries are written to a memory where each index entry includes a word entry representing a unique indexable portion of information, and one or more location entries for each occurrence of the unique indexable portion information. The index entries are sorted according to a collating order of the word entries, and sequentially according to the location entries of each index entry. A query is parsed to generate a first term and a second term related by an AND logical operator, the AND operator requires that a first index entry corresponding to the first term and a second index entry corresponding to the second term both have locations in the same record to satisfy a query.

Abstract: A method and apparatus for enabling access of a document on a remote network device by a local computer includes an interceptor for intercepting a request (from a web browser on the local computer system) for accessing the document. The interceptor responsively ascertains whether the local computer is connected to a network and, if connected to the network, downloads the document into memory of the local computer system. If the local computer is not connected to the network, the method and apparatus locates the document in the local memory of the local computer. Once downloaded or located, whichever the case may be, the document may be utilized by the user, such as by displaying the document on a display device.

Abstract: A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

Abstract: A new pseudo network adapter is disclosed providing an interface for capturing packets from a local communications protocol stack for transmission on the virtual private network. The system further includes a Dynamic Host Configuration Protocol (DHCP) server emulator, and an Address Resolution Protocol (ARP) server emulator. The new system indicates to the local communications protocol stack that nodes on a remote private network are reachable through a gateway that is in turn reachable through the pseudo network adapter. The new pseudo network adapter includes a transmit path for processing data packets from the local communications protocol stack for transmission through the pseudo network adapter. The transmit path includes an encryption engine for encrypting the data packets and an encapsulation engine for encapsulating the encrypted data packets into tunnel data frames.

Abstract: In a computerized method, a set of radial distortion parameters are recovered from a single image by selecting arbitrarily oriented straight lines in a single image using an input device. Then, objective functions in Cartesian form are minimized using a least-squares fit formulation to recover the set of radial distortion parameters.

Abstract: A semi-mobile desktop personal computer incorporating the features of a desktop personal computer with the mobility of a mobile personal computer. The computer includes a system enclosure attached to a storage enclosure, the storage enclosure extends outside the system enclosure and provides stability for the system enclosure by engaging the surface on which the system enclosure has been placed for use.

Abstract: A client-server network including a number of client computer systems, each of the client computer systems having a network interface, a number of server computer systems, each of the server computer systems having a network interface, and a replicator system connecting the client computer systems to the server computer systems, the replicator system transparently processing a number of requests from the client systems to a number of services resident in the server systems.

Abstract: A method and apparatus for performing error detection in a network is disclosed. An error counter is stored in a common memory location accessible by all nodes. The error counter includes separate partitions associated with each node in the network. Each partition includes two error counter values representing, respectively, sending and transmission error counts, for a corresponding node. No global locking mechanism is required to synchronize access to the commonly accessed error counter. Rather, access to the error counter is provided by having code executing on each node adhering to rules regarding the types of access to the various partitions in the error counter. Each node may read from any partition, but may only write to its own partition.

Abstract: A computer implemented method for filtering mail messages in a distributed computer system. The distributed mail service system includes a plurality of client computers connected to a mail service system via a network. Mail messages are stored in message files of the mail service system. Each mail message is parsed and indexed to generate a full-text index of the mail service system. A query is composed, the query includes terms and operators. The query is stored in the mail service system as a named filter query. A new mail message received by the mail service system is parsed, indexed and searched to determine if the content of the new mail message does not match on the named filter query, in which case an inbox label and an unread label to the new mail message.

Abstract: In a method for scheduling instructions executed in a computer system including a processor and a memory subsystem, pipeline latencies and resource utilization are measured by sampling hardware while the instructions are executing. The instructions are then scheduled according to the measured latencies and resource utilizations using an instruction scheduler.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: A technique reduces the latency of a memory barrier (MB) operation used to impose an inter-reference order between sets of memory reference operations issued by a processor to a multiprocessor system having a shared memory. The technique comprises issuing the MB operation immediately after issuing a first set of memory reference operations (i.e., the pre-MB operations) without waiting for responses to those pre-MB operations. Issuance of the MB operation to the system results in serialization of that operation and generation of a MB Acknowledgment (MB-Ack) command. The MB-Ack is loaded into a probe queue of the issuing processor and, according to the invention, functions to pull-in all previously ordered invalidate and probe commands in that queue. By ensuring that the probes and invalidates are ordered before the MB-Ack is received at the issuing processor, the inventive technique provides the appearance that all pre-MB references have completed.

Abstract: A debugger for debugging, from a central location (e.g., a user terminal 13), jobs or processes running on one or more remote units (11) connected to the user terminal (13) via a communication network (15). The user terminal (13) includes a debugger (21) that receives and interprets debug commands produced by a keyboard and display console (19). The debug commands fall in any one of three categories--debug commands directed to the user terminal (USER TERMINAL CONTROL commands); debug commands directed to a particular remote unit (REMOTE UNIT CONTROL commands); and, debug commands directed to a specific job or process of multiple jobs or processes running on a particular remote unit (LOCAL JOB/PROCESS commands). The USER TERMINAL CONTROL commands are executed at the user terminal (13). The REMOTE UNIT CONTROL commands and LOCAL JOB/PROCESS commands are transmitted to the remote units (11) via the communication network (15).