Abstract: A method of managing computer memory pages. The sharing of a program-accessible page between two processes is managed by a predefined mechanism of a memory manager. The sharing of a page table page between the processes is managed by the same predefined mechanism. The data structures used by the mechanism are equally applicable to sharing program-accessible pages or page table pages.

Abstract: A cache includes an address cache for storing memory addresses. An address queue is connected to the address cache for storing missed addresses in the order that the address cache is probed. A memory controller receives the missed addresses from the address queue. A data queue receives data stored at the missed addresses from the memory controller. A probe result queue is connected to the address cache for storing data cache line addresses and hit/miss information. A multiplexer connected to the data cache, the data queue, and the probe result queue selects output data from the data cache or the data queue depending on the hit/miss information.

Abstract: A high-speed CMOS latch includes at each storage node a pull-up P-transistor with its gate tied to a dynamic node, and a pull-down N-transistor with its gate controlled by the inverse of the states of the remaining dynamic nodes. The P-transistor drives the storage node high to VDD, and the N-transistor drives the node low to VSS, as appropriate. During evaluation, one dynamic node discharges to a low state and in response each storage node is driven relatively quickly to the desired high or low state through either the associated pull-up or pull-down transistor. Precharging P-transistors drive the dynamic nodes high during precharge periods. As the dynamic nodes go high, they turn off all of the pull-up and pull-down transistors that drive the latch storage nodes, and the latch retains the evaluated state of the dynamic nodes until the start of the next evaluation cycle. Accordingly, the latch does not require a separate clock.

Abstract: Using an input device of a computer system, a graphic drawing is defined to include at least one graphic component. The graphic component is subject to a plurality of constraints. At least one of the constraints is redundant with respect to the other constraints. Approximate linear equations are substituted for the constraints. A subset of the equations are selected to determine a converging solution for the redundantly constrained graphic drawing.

Abstract: A method of encoding a message including a plurality of data items, includes identifying maximum and minimum numbers of first edges to be associated with data items. A first distribution of different numbers of first edges, ranging from the maximum to the minimum number of first edges, to be associated with the data items is computed. A first associated number of first edges, within the range, is established for each data item, the different numbers of first edges being associated with the data items according to the computed first distribution. A maximum and minimum number of second edges to be associated with redundant data items are identified. A second distribution of numbers of second edges, ranging from the maximum to the minimum number of second edges, to be associated with the redundant data items is computed.

Abstract: In a computerized method for predicting a particular user preference for an item based on observations made about the item by other users, client computers are used to enter the observations about the items. The observations are forwarded to a server computer via a network. The observations are collected in a database of the server computer. Using factor analysis, a solver module of the server computer analyzes the observations to generate a model of the observations. The models are distributed to the client computers via the network. The client computer makes predictions of preferences of the particular user using the models.

Abstract: A circuit which protects an integrated circuit (IC) device from damage due to electrostatic discharge (ESD). The protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit. The source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage. During normal operation of the IC, the gate modulation circuit disables the MOSFET clamp by connecting its gate terminal to a ground reference voltage. This permits signal voltages to pass between the I/O pad and any operating circuits connected to the pad. During an ESD event, the gate modulation circuit connects the gate to the I/O pad, which enables the MOSFET clamp, causing any ESD voltages and resulting currents to be shunted through the MOSFET clamp to ground. As a result, the ESD clamp reaches its clamped-to snapback voltage via an increase in MOSFET channel current, and not via junction breakdown.

Abstract: A computer implemented method provides access to processes and data using strengthened password. During an initialization phase, an access code is stored in a memory of a computer system. The access code is an application of a one-way hash function to a concatenation of a password and a password supplement. The size of the password supplement is a fixed number of bits. During operation of the system, a user enters a password, and the one-way hash function is applied to concatenations of the password and possible values having the size of the password supplement to yield trial access codes. Access is granted when one of the trial access codes is identical to the stored access code.

Abstract: A data processing system includes at least one central processor for executing instructions of software programs. In addition the data processing system includes a memory containing a data structure common to the software programs. The common data structure includes a compressed index data structure. The index structure stores index entries referencing a database. The database includes multiple records, each having a unique address in the database. Each index entry includes a word entry if the index entry represents a compressed encoding of a unique portion of information sequentially parsed from the database. The word entry is followed by one or more location entries which reference occurrences of the portions of information. Each index entry includes a metaword entry if the index entry represents a unique attribute of one or more related words. The metaword entry is followed by one or more location entries referencing occurrences of the attributes.

Abstract: A relatively small FIFO queue is located on a semiconductor chip receiving and transmitting data in a computer system, typically a computer network. The FIFO queue has additional storage capability in the form of an expansion into the local memory of the computer system. The front and back ends of the FIFO, which are involved in receiving and transmitting data, are implemented on the chip. The FIFO expands into the space provided in the local memory only when the on-chip portion of the FIFO is full. The middle portion of the FIFO resides in expansion in the local memory. The local memory is accessed only in bursts of multiple credits, both for read transactions and for write transactions.

Abstract: A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: In a computerized method, text segments of a text file are aligned with audio segments of an audio file. The text file includes written words, and the audio file includes spoken words. A vocabulary and language model are generated from the text segment. A word list is recognized from the audio segment using the vocabulary and language model. The word list is aligned with the text segment, and corresponding anchors are chosen in the word list and text segment. Using the anchors, the text segment and the audio segment are partitioned into unaligned and aligned segments according to the anchors. These steps are repeated for any unaligned segments until a termination condition is reached.

Abstract: In a modular tower building block system for containing computing system devices, an I/O bus is incorporated into the modular blocks of the building block system by using a printed circuit board to carry the I/O bus in each modular block. The printed circuit board is mounted and positioned in each modular block to electrically connect with a printed circuit board in a next adjacent modular block when two modular blocks are stacked on each other. Also, there are a plurality of I/O buses on the printed circuit boards and only one I/O bus is distributed from each modular block. The printed circuit board is precisely located in each modular block at a predetermined position. Alignment pins and receivers provide alignment between stacked modular blocks to precisely position one modular block to the other modular block. This also aligns electrical connectors on the printed circuit boards of the stacked blocks so that the connectors on the printed circuit boards from two blocks mate when the two blocks are stacked.

Abstract: A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus configuration. The technique assigns a code consisting of predetermined number of asserted bits to each portion of the memory. If a failure condition is detected, the code associated with that portion is asserted onto the bus. Because the code for each memory portion always has a given number of asserted bits, a multi-bit failure situation can be distinguished from a single bit failure situation by counting the number of bits asserted.

Abstract: A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison.

Abstract: A method is provided for estimating execution rates of program executions paths. The method samples path-identifying state information of selected instructions while executing the program in a processor. A control flow graph of the program is supplied, the control flow graph includes a plurality of path segments. The control flow graph is analyzed using the path-identifying state information to identify a set of path segments that are consistent with the sampled state information. The set of paths segments can be counted to determine their relative execution frequencies.

Abstract: A method for searching a plurality of index entries in an index of a database including parsing a query into one or more terms with an operator, generating a basic stream reader object to sequentially read the location of the index to determine a target location for the term, and generating a compound stream reader object to reference the plurality of basic stream reader objects associated with the term related by the operator to produce locations of words within a single record.

Abstract: An apparatus sums a plurality of columns of binary bits to produce a plurality of partial sum and carry bits. The bits of a particular column being of the same order of magnitude, and the bits of different columns differing in orders of magnitude. The apparatus includes one or more full adder. Each full adder receives three bits as an input to produce a first sum bit and a first carry bit as output. The apparatus also includes one or more half adders. Each half adder receives two bits as input to produce a second sum bit and a second carry bit as output. The full adders and half adder are interconnected as a plurality of interconnecting column adders. Each column adder sums bits of the input of at least one column and generates a partial sum and carry bit. Each column adder has a plurality of stages. A plurality of conductors interconnect the stages of each column adder with other stages in the same column adder and with stages in other adjacent column adders.

Abstract: A virtual memory system includes a virtual address space including a process private space, a shared space, and a page table space located between the process private space and the shared space. The page table space includes page table entries mapping both the process private space and the shared space to physical memory. The page table entries might include a set of virtually contiguous process private page table entries adjacent to the process private space, and a set of virtually contiguous shared page table entries adjacent to the shared space. The process private space may include virtual addresses on a first side of a private/shared virtual address boundary, and the shared space includes virtual addresses on a second side of the private/shared virtual address boundary.

Abstract: In response to a command by a local computer system, a copy of a remote document is downloaded onto a remote update network device from an origin network device. A predetermined time after the remote document copy is downloaded, the update network device interfaces with the origin network device to compare the remote document with the remote document copy. If the remote document has been modified since it was copied onto the update network device, the remote document copy is updated to reflect the modifications. When the local computer system reconnects to the network, the updated remote document copy may be downloaded into the memory of the local computer system if the remote document copy on the update network device is different than a local copy of the remote document stored in the local computer system.