Abstract: An adaptive receiver includes an adaptive decoder for providing decoded output data from a video signal encoded for satellite, terrestrial or cable transmission. The apparatus includes an adaptive decoder for providing a first decoded output as a function of a code rate selected from a plurality of code rates. The apparatus also includes an adaptive deinterleaver for deinterleaving the first decoded output in accordance with a deinterleaving function selected from a plurality of deinterleaving functions. In addition, the apparatus includes an output signal processor for processing the deinterleaved output data to provide the decoded output data. The demodulator may also incorporate a an adaptive error decoder for detecting and correcting errors in the deinterleaved output. In addition, a signal quality detector may provide an estimate of the error in the decoded output data. The apparatus is automatically configured to be compatible with the encoded video signal format in response to the error estimate.

Abstract: A method for identifying those process steps which produce "high risk" particulate contamination that is most likely to produce defects. The die positions of particulate deposits on a wafer are measured prior to and subsequent to a specific process step, to determine the die positions of particulate deposits introduced during that specific process step. Then, subsequent electrical tests of the wafer are used to determine which locations on the wafer contain faulty circuitry. The locations of particulate deposits introduced during the specific process step are then correlated to the locations of faulty circuitry. The result is a measure of the extent to which particulate deposits introduced during the specific process step contribute to reductions in yield of the manufacturing process.

Abstract: Interface logic for interfacing a processor to a memory unit is disclosed. The interface logic in one embodiment of the present invention uses a single port to both receive an address from the processor and drive a multiplexed address to the memory unit. By causing the processor to relinquish control of the address bus, the interface logic can drive an address over the same lines used by the processor to communicate the address to the interface logic. This procedure eliminates the need for two ports, and therefore reduces the pin count of the interface logic. For example, in a non-paging implementation, an interface bus is connected to a row portion of the address bus. The processor drives the row address over the row portion of the address bus and thereby also over the interface bus to the memory unit.

Abstract: A two-way paging system includes a paging terminal and one or more transmitters and receivers. The paging terminal, transmitter and receiver are synchronized to a common clock reference which is derived from the global positioning satellite system. The transmitter transmits paging signals in sequential frames having a predefined start time and duration. A paging unit is instructed to transmit its acknowledge signal during a predefined time slot. By synchronizing the paging terminal transmitters and receivers to a common clock the receivers are able to determine the frame number and time slot during which an acknowledge signal is transmitted based on the time of reception of the acknowledge signal. If the acknowledge signal is transmitted during the correct flame and time slot, the paging system can determine that the paging unit has received the paging message correctly.

Abstract: A wrist-worn paging receiver provides an incoming message alarm by contacting the wrist of the user by the use of rotating cam lobes that reside inside the paging receiver and that are separated from actual contact with the user's skin by a thin, flexible membrane. Various alarm modes are provided by controlling the ratio of the period of rotation to period of rest of the cam lobes mounted on a cam shaft that is driven by an electric motor inside the paging receiver.

Abstract: A washing net attaching and detaching structure of a fully automatic washing machine with a washing course of dry-marked clothes is shaped as a basket which is attachably and detachably installed within a washtub for being vibrated in the up and down directions in accordance with a reciprocal ascending and descending movement of a driving member to preserve and wash laundry indicated with a dry mark. The washing net has a diameter smaller than an inner circumference of an upper end of the washtub for being easily attached and detached to and from the washtub during the cleaning of dry-marked clothes to provide a convenience to a user and prevent damage to the laundry caused by the laundry being bitten in the lower portion of the washing net, thereby significantly improving the efficiency and reliability of the product.

Abstract: A video clock input signal is applied to a delay line comprising a cascade connection of a plurality of delay elements formed in an integrated circuit for providing a plurality of delayed clock signals at respective taps of the delay line. A selection circuit, responsive to a horizontal synchronizing signal supplied thereto, couples a selected one of the taps to an output for providing a delayed output clock signal that is edge-aligned with the synchronizing signal. For reducing the number of taps required to provide a given minimum delay step resolution and a given minimum total delay for delay elements which may vary in delay, from one integrated circuit to another, the taps are spaced one element apart for a first group of the delay elements and are spaced more than one element apart for at least one second group of the elements.

Abstract: A rotary transformer circuit, for a video cassette recorder, including: a single rotary transformer; a plurality of magnetic heads for recording/playing back signals on the magnetic tape; and a switching circuit for selectively sampling each of the plurality of magnetic heads and for forming a signal of concatenated individual-head sub-signals and for selectively connecting a signal of concatenated individual-head sub-signals to corresponding ones of the plurality of magnetic heads. The switching circuit transferring the signal of concatenated individual-head sub-signals through the single rotary transformer. The circuit avoids noise caused by cross-talk when using multiple rotary transformers.

Abstract: A memory module is described which can be programmed with module information, identifying the type and size of the memory module, after completed assembly of the memory module. The memory module includes a plurality of edge connectors for electrically connecting the memory module circuitry external to the memory module, and a plurality of DRAM memory devices electrically connected to corresponding edge connectors for receiving and providing data from and to the external circuitry. The memory module also includes a Serial EEPROM for storing the module information. The Serial EEPROM has a Serial Data pin connected to a first of the edge connectors for providing the module information to the external circuitry. The Serial EEPROM has a Write Control pin for receiving an enabling signal which selectively enables the operation of the Serial EEPROM in Write or Read-Only mode. The memory module further includes interface circuitry which couples the Write Control pin with a second and a third of the edge connectors.

Abstract: A reproducing apparatus for a DVCR having a reverse operation function includes a data restoring portion for restoring a serial clock and reverse-serial data from an input signal; a servo portion for outputting a reverse-playback signal; an ID detector for detecting an ID to thereby output first and second segment end signals; and a sync signal detector for detecting a block sync signal and a signal indicative of an initial position of a track for reverse playback, using the serial clock and reverse-serial data from the data restoring portion and the first and second segment end signals from the ID detector. The reproducing apparatus enables reverse playback as well as reverse playback skip play.

Abstract: A chip mounting plate construction of lead frames for semiconductor packages which provides a chip mounting plate having a greatly reduced area to obtain a small bonding area between the chip mounting plate and a semiconductor chip mounted on the chip mounting plate, thereby capable of minimizing thermal strain generated at the chip mounting plate due to a thermal expansion thereof. The chip mounting plate is constructed to have a smaller area than the semiconductor chip, to have a central opening, or to have recesses.

Abstract: A device, which is adapted to be connected to an electronic apparatus, is capable of having a non-rechargeable battery pack or a rechargeable battery pack connected thereto. The battery packs supply a driving voltage to the electronic apparatus when connected to the device. The device can have an external power source attached thereto for energizing the electronic apparatus by a DC voltage, for disabling the driving voltage supplied by the battery packs and for supplying a charging voltage to the device and to the rechargeable battery pack. The device automatically discriminates between the rechargeable battery pack and the non-rechargeable battery pack so that the charging voltage from the external power source is only applied to the rechargeable battery pack and not to the non-rechargeable battery pack.The rechargeable battery pack includes a casing having a positive electrode and a negative electrode mounted thereon and a non-conductive insulating member which is connected to the casing.

Abstract: A circuit in accordance with an inventive arrangement comprises: a signal generator for a correction signal having a substantially parabolic shape at a scanning rate of the video display; a waveform clipper coupled to the signal generator for the correction signal, the waveform clipper having a current sink transistor coupled to the signal generator for the correction signal for clamping the correction signal, and a reference transistor coupled to a base of the current sink transistor for providing a reference voltage; and, a switch for disabling the reference transistor during excursions of the correction signal and enabling the reference transistor during clamping. The switch may comprise a switching transistor coupled to the reference transistor and to the correction signal, the switching transistor disabling the reference transistor during excursions of the correction signal and enabling the reference transistor during clamping.

Abstract: A light amount controlling apparatus includes a light source for producing light and a light source driver for driving the light source. A zoom lens unit includes a zoom lens for varying an angle of projection of the light, and a zoom lens position detector detects a position of the zoom lens. A memory stores control data corresponding to the position of the zoom lens and a memory controller reads the control data from the memory according to a detected value of the zoom lens position of the zoom lens position detector. A controller controls the light source driver to vary an amount of light projected from the light source in accordance with the control data output from the memory controller.

Abstract: An idler gear transfer control apparatus for a reel drive apparatus of a VCR, is disclosed, wherein the VCR includes a reversible motor, a base, a shaft disposed at the base, an input gear rotatably disposed on the shaft for receiving a driving force from the motor, and an idler arm having one end rotatably connected to the shaft and another end carrying an idler gear connected to the input gear, the idler arm being movable about the shaft for engaging the input gear, the idler arm being movable about the shaft for engaging the idler gear selectively with a supply reel gear or a take-up reel gear, whereby the driving force of the motor is selectively transferred to the supply reel gear or the tape-up reel gear in accordance with a rotation direction of the input gear.

Abstract: A system for processing auxiliary video signals provides for decoding an extended data services signal in line 21 of field 2. Extended data services provide a general purpose video system information and control capability in addition to basic closed caption operation. Extended data services information is arranged in packets of data. Each packet provides information regarding current of future video programs, the source of the video program, and miscellaneous information such as time of day. The extended data services data may be decoded to control the operation of a video system including a videocassette recorder (VCR) and a television receiver.

Abstract: A tiltable, rotatable and detachable LCD view finder for a camcorder that enables a user to easily take pictures while viewing the LCD viewfinder. The viewfinder can be rotated 360.degree. and tilted 180.degree. relative to the upper surface of the camcorder body. The viewfinder system includes: an LCD (Liquid Crystal Display) viewfinder; a downwardly opened recess formed on a predetermined edge portion of said LCD viewfinder and having a first side wall, a second side wall, a back wall and a semicircular end; and a tiltable, rotatable and detachable compound joint assembly member fitted into said recess for tiltably, rotatably and detachably connecting the LCD viewfinder, whereby the LCD viewfinder can be tilted, rotated, and detached relative to the camcorder body.

Abstract: A method and apparatus for detecting and indicating the number of times a CRT unit arcs. The apparatus is constructed of a ferrite split toroid core wound with wire which is coupled around the focus lead and/or ground lead of a CRT through which a current spike will occur during an arcing event. The wound wire is coupled to a current pulse detector which in turn is coupled to a monostable mode timer and counter for counting the number of arcing events. The counter is coupled to a display device for displaying the number of times the CRT has arced.