Patents Assigned to Elpida Memory, Inc.
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Publication number: 20120122251Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.Type: ApplicationFiled: November 10, 2011Publication date: May 17, 2012Applicant: Elpida Memory Inc.Inventors: Junji YAMADA, Hiroaki IKEDA, Kayoko SHIBATA, Yoshihiko INOUE, Hitoshi MIWA, Tatsuya IJIMA
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Publication number: 20120120745Abstract: A semiconductor device includes: an input node supplied with an input signal; an output node provided correspondingly to the input node; first and second input circuits coupled in parallel to each other between the input and output nodes; and a control circuit configured to control the first and second input circuits such that one of the first and second input circuits is switched over from an active state to an inactive state and the other of the first and second input circuits is switched over from an inactive state to an active state during the one of the first and second input circuits being still in the active state.Type: ApplicationFiled: October 24, 2011Publication date: May 17, 2012Applicant: Elpida Memory, Inc.Inventors: Kazutaka Miyano, Hiroyuki Inage
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Patent number: 8178428Abstract: A manufacturing method of a semiconductor device is provided, comprising: loading a substrate into a processing chamber; forming a first film on the substrate by supplying silicon atom-containing gas, boron atom-containing gas, and germanium atom-containing gas into the processing chamber; forming a second film on the first film by supplying the silicon atom-containing gas and the boron atom-containing gas into the processing chamber; and unloading the substrate from the processing chamber.Type: GrantFiled: January 28, 2010Date of Patent: May 15, 2012Assignees: Hitachi Kokusai Electric Inc., Elpida Memory, Inc.Inventors: Takaaki Noda, Jie Wang, Kazuaki Tonari, Satoru Sugiyama
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Patent number: 8179709Abstract: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.Type: GrantFiled: August 22, 2008Date of Patent: May 15, 2012Assignee: Elpida Memory, Inc.Inventor: Sumio Ogawa
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Patent number: 8178971Abstract: A ball grid array semiconductor device has a wiring substrate (2), a semiconductor chip (6) disposed on one surface side of the wiring substrate, and a bump arrangement (5) as external terminals disposed on a surface side, opposite to the one surface side, of the wiring substrate. The semiconductor chip is mounted so that the center of the semiconductor chip is shifted from the center of the semiconductor device by one pitch or more of the bump arrangement, and the bump arrangement has a reinforcing structure (5-2) for a bump array located at a position farthest from the center of the semiconductor device in a shift direction of the semiconductor chip.Type: GrantFiled: March 4, 2009Date of Patent: May 15, 2012Assignee: Elpida Memory, Inc.Inventor: Seiya Fujii
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Publication number: 20120112563Abstract: A semiconductor device includes a first circuit, a second circuit, a first wire, and a pair of shield lines. The first circuit includes a voltage generating circuit generating a predetermined voltage and produces the predetermined voltage at an output end thereof. The first wire connects the output end of the first circuit to an input end of the second circuit. The pair of shield lines is disposed so as to sandwich the first wire therebetween. One of the shield lines is supplied with a power supply potential for driving at least one of the voltage generating circuit and the second circuit. Another of the shield lines is supplied with a ground potential for driving at least one of the voltage generating circuit and the second circuit.Type: ApplicationFiled: November 4, 2011Publication date: May 10, 2012Applicant: Elpida Memory, Inc.Inventors: Taihei SHIDO, Mototsugu FUJIMITSU, Nobuhiro OODAIRA, Naoki KITAI
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Publication number: 20120113736Abstract: A semiconductor device of the invention comprise a memory cell array configured with hierarchical local bit lines and global bit lines, in which there are provide local bit lines, global bit lines, switches controlling a connection between the global bit lines, sense amplifiers, and a control circuit controlling the switches. In a first period, each sense amplifier amplifies a signal of one of adjacent global bit lines, and in a second period, each sense amplifier amplifies a signal of the other thereof. Accordingly, coupling between the global bit lines can be suppressed.Type: ApplicationFiled: November 2, 2011Publication date: May 10, 2012Applicant: Elpida Memory Inc.Inventor: Kazuhiko Kajigaya
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Publication number: 20120113735Abstract: A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential supplied to the bit line are controlled so that the first potential applied to a gate of the first transistor is between the second and third potentials, the second potential is set larger than the third potential, and a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential is smaller than the third potential and higher than a low potential supplied to the second transistor. A potential of the bit line transitions from the third potential toward the low potential in accordance with data of a current change memory cell.Type: ApplicationFiled: November 2, 2011Publication date: May 10, 2012Applicant: Elpida Memory Inc.Inventor: Kazuhiko Kajigaya
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Publication number: 20120115300Abstract: In a method for manufacturing a semiconductor memory device, a three dimensional lower electrode including a titanium nitride film is formed on a semiconductor substrate, and a dielectric film is formed on the surface of the lower electrode. After a first upper electrode is formed at a temperature that the crystal of the dielectric film is not grown on the surface of the dielectric film, the first upper electrode and the dielectric film are heat-treated at a temperature that the crystal of the dielectric film is grown to convert at least a portion of the dielectric film into a crystalline state. Thereafter, a second upper electrode is formed on the surface of the first upper electrode.Type: ApplicationFiled: October 27, 2011Publication date: May 10, 2012Applicant: Elpida Memory, Inc.Inventors: Toshiyuki Hirota, Takakazu Kiyomura
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Patent number: 8174915Abstract: A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is changed from the first frequency to a second frequency higher than the first frequency. The device performs the first operation in synchronization with the clock signal of the second frequency following changing the frequency of the clock signal.Type: GrantFiled: February 2, 2010Date of Patent: May 8, 2012Assignee: Elpida Memory, Inc.Inventor: Akiyoshi Yamamoto
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Patent number: 8173515Abstract: An oxide film and a liner film are formed on an inner wall of a trench in a semiconductor substrate. After filling an SOD film in the trench, a heat treatment is carried out. Part of the liner film in contact with the SOD film is removed to expose part of the SOD film. A heat treatment is carried out on the SOD film. An isolating region is formed by filling an insulating film in the trench.Type: GrantFiled: July 2, 2009Date of Patent: May 8, 2012Assignee: Elpida Memory, Inc.Inventors: Toshiya Nakamori, Hiroshi Kujirai
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Patent number: 8174907Abstract: To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first, second, and third buffers to the second bus line; fifth to eighth banks connected via the fourth and fifth buffers to the second bus line; and a data input/output unit connected to the second bus line. Transfer delay times of the fourth and fifth buffers are longer than transfer delay times of the first, second, and third buffers. Thereby, it becomes possible to eliminate differences in data transfer times resulting from differences in distances between far and near ends without causing significant increase in wire density, increase in power consumption, or the like.Type: GrantFiled: April 20, 2010Date of Patent: May 8, 2012Assignee: Elpida Memory, Inc.Inventors: Takuyo Kodama, Yoji Idei
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Patent number: 8174068Abstract: A semiconductor device includes: a semiconductor substrate; a silicon pillar provided perpendicularly to a main surface of the semiconductor substrate; a gate dielectric film that covers a portion of a side surface of the silicon pillar; an insulator pillar that covers remaining portions of the side surface of the silicon pillar; a gate electrode that covers the silicon pillar via the gate dielectric film and the insulator pillar; an interlayer dielectric film provided above the silicon pillar, the gate dielectric film, the insulator pillar, and the gate electrode; and a gate contact plug embedded in a contact hole provided in the interlayer dielectric film, and in contact with the gate electrode and the insulator pillar. A film thickness of the insulator pillar in a lateral direction is thicker than a film thickness of the gate dielectric film in a lateral direction.Type: GrantFiled: July 8, 2010Date of Patent: May 8, 2012Assignee: Elpida Memory, Inc.Inventor: Kazuhiro Nojima
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Publication number: 20120106229Abstract: To include stacked plural core chips, each of which includes a first through silicon via for transferring write data and a second through silicon via for transferring read data, and an interface chip commonly connected to the core chips. The interface chip includes a data input/output terminal, an input buffer provided between the data input/output terminal and the first through silicon via, and an output buffer provided between the data input/output terminal and the second through silicon via. With this configuration, the write data and the read data are transferred through the different through silicon vias, whereby the collision of data is not caused even when continuous accesses are made to different ranks.Type: ApplicationFiled: October 12, 2011Publication date: May 3, 2012Applicant: Elpida Memory, Inc.Inventor: Chikara Kondo
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Publication number: 20120109561Abstract: A wafer test apparatus, comprises: a storage unit that stores a first test program including a plurality of first operation test programs and a second test program including a plurality of second operation test programs; and a calculation unit that executes the first test program on at least one of wafers in a lot and outputs accumulated information about a defective memory cell(s) included in the wafer to the outside thereof when each operation test of the plurality of first operation tests is completed, and executes the second test program on remaining wafers in the lot and outputs accumulated information about a defective memory cell(s) included in the wafer to the outside thereof when all the operation tests in the plurality of second operation tests are completed.Type: ApplicationFiled: October 28, 2011Publication date: May 3, 2012Applicant: Elpida Memory, Inc.Inventor: Satoru Terui
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Patent number: 8169089Abstract: A semiconductor device includes at least bonding wires between electrode pads on a main surface of a semiconductor chip and connection pads on a wiring board. The wires form loop shapes from the electrode pads of the semiconductor chip. The semiconductor device also includes at least forming flat parts on the loop-shaped wires, and using a sealing material to seal the semiconductor chip such as to bury the flat parts.Type: GrantFiled: June 16, 2009Date of Patent: May 1, 2012Assignee: Elpida Memory, Inc.Inventor: Toshihiko Usami
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Patent number: 8169015Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.Type: GrantFiled: May 6, 2008Date of Patent: May 1, 2012Assignee: Elpida Memory, Inc.Inventor: Toshiyuki Hirota
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Publication number: 20120098145Abstract: A semiconductor device includes a chip stacked structure. The chip stacked structure may include, but is not limited to, first and second semiconductor chips. The first semiconductor chip has a first thickness. The second semiconductor chip has a second thickness that is thinner than the first thickness.Type: ApplicationFiled: December 29, 2011Publication date: April 26, 2012Applicant: Elpida Memory, Inc.Inventors: Masanori Yoshida, Katsumi Sugawara
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Publication number: 20120098115Abstract: A semiconductor device has a substrate, a semiconductor chip mounted on the substrate, an encapsulating body encapsulating the semiconductor chip on the substrate, and a plurality of heat sink plates embedded in the encapsulating body so as to have a surface that is exposed to an exterior of the encapsulating body and positioned on the same plane. The heat sink plates are spaced from each other.Type: ApplicationFiled: October 7, 2011Publication date: April 26, 2012Applicant: Elpida Memory, Inc.Inventor: Yuji Watanabe
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Publication number: 20120100682Abstract: A manufacturing method of a semiconductor device includes the steps of: forming an insulating pillar on the main surface of a silicon substrate; forming a protective film on the side surface of the insulating pillar; forming a silicon pillar on the main surface of the silicon substrate; forming a gate insulating film on the side surface of the silicon pillar; and forming first and second gate electrodes so as to contact each other and so as to cover the side surfaces of the silicon pillar and insulating pillar, respectively. According to the present manufacturing method, the protective film is formed on the side surface of the insulating pillar as a dummy pillar, thus preventing the dummy pillar from being eroded when the silicon pillar for channel is processed into a transistor. Therefore, it is possible to reduce a probability of occurrence of gate electrode disconnection.Type: ApplicationFiled: October 5, 2011Publication date: April 26, 2012Applicant: Elpida Memory, Inc.Inventors: Yuki Munetaka, Yoshihiro Takaishi