Patents Assigned to Elpida Memory, Inc.
  • Semiconductor device
    Patent number: 8233344
    Abstract: A semiconductor device includes a plural number of sense amplifiers that sense at least two data in parallel and that operate under a first frequency, and a multiplexer that operates under a second frequency higher than the first frequency and that sequentially serially outputs the data sensed in parallel. The semiconductor device also includes a driver circuit having a latch circuit connected to an output of the multiplexer, and an output driver circuit connected to the latch circuit and operating under the second frequency. The voltage of a power supply of the sense amplifiers is the same as the voltage of a power supply of the output driver circuit. The power supply of the sense amplifiers and the power supply of the output driver circuit are connected to respective different power supply lines.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: July 31, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Noriaki Mochida
  • SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE
    Publication number: 20120187402
    Abstract: A semiconductor device includes a semiconductor chip having first and second surfaces. A first through electrode extends through the semiconductor chip. A first surface electrode is positioned on the first surface of the semiconductor chip and coupled to a first end of the first through electrode. A second surface electrode is positioned on the second surface of the semiconductor chip. The second surface electrode is coupled to a second end of the first through electrode. A second through electrode extends through the semiconductor chip and has third and fourth ends. A third surface electrode is positioned on the second surface of the semiconductor chip and is coupled to the fourth end of the second through electrode. The semiconductor device is free of a surface electrode on the first surface of the semiconductor chip and is coupled to the third end of the second through electrode.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 26, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Masahiro YAMAGUCHI, Hiroaki Ikeda
  • SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER
    Publication number: 20120182778
    Abstract: Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals, and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection.
    Type: Application
    Filed: January 10, 2012
    Publication date: July 19, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Homare SATO
  • SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER
    Publication number: 20120182822
    Abstract: Such a device is disclosed that includes a first chip outputting a bank address signal and an active signal, and a plurality of second chips stacked on the first chip. Each of the second chips includes a plurality of memory banks each selected based on the bank address signal. Selected one or ones of the memory banks is brought into an active state in response to the active signal. Each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state. The first chip activates a bank active signal when at least one of the local bank active signals is activated.
    Type: Application
    Filed: January 10, 2012
    Publication date: July 19, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Junichi HAYASHI
  • Manufacturing method of semiconductor device
    Patent number: 8222159
    Abstract: A manufacturing method of semiconductor device comprises: sequentially laminating a third mask layer, a second mask layer, and a first mask layer on a processed layer; forming a fourth mask layer on the first mask layer; processing the first mask layer so as to have a line pattern form using the fourth mask layer as a mask; removing the first mask layer; processing the second mask layer so as to have a pair of line pattern forms using the pair of sidewall layers as a mask; forming a fifth mask layer on the third mask layer; forming a pair of opening portions in the third mask layer using the fifth mask layer as a mask; and forming a pair of groove portions on the processed layer using the third mask layer as a mask.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: July 17, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Takashi Sugimura
  • Semiconductor device having a complementary field effect transistor
    Patent number: 8222952
    Abstract: A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: July 17, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Shinichi Miyatake, Seiji Narui, Hitoshi Tanaka
  • BGA semiconductor device having a dummy bump
    Patent number: 8222737
    Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: July 17, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yuji Watanabe, Hisashi Tanie, Koji Hosokawa, Mitsuaki Katagiri, Ichiro Anjo
  • Semiconductor memory device
    Patent number: 8223536
    Abstract: A semiconductor memory device comprises: a phase change element (RP) and a memory cell transistor (MN0) that controls writing and reading of data with respect to the phase change element (RP); the memory cell transistor (MN0) supplies a current to the phase change element (RP) based on a first potential (VPS) in a first (read) operation mode, and in a second (write) operation mode supplies a current based on the first potential (VPS), and subsequently supplies a current based on a second potential (VPP) higher than the first potential (VPS). In a write operation, consumed current is reduced.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: July 17, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yasuko Tonomura, Shuichi Tsukada
  • CMP apparatus and method of polishing wafer using CMP
    Patent number: 8221191
    Abstract: A CMP apparatus is provided with a polishing pad, a film thickness sensor for measuring a thickness of a film being polished on a wafer via the polishing pad, a polishing pad thickness measuring unit for measuring the thickness of the polishing pad, a dresser for dressing the polishing pad, and a polishing control unit for switching polishing conditions in response to a fact that an output value from the film thickness sensor has exceeded a threshold value. The polishing control unit has a memory unit for storing a threshold value corresponding to the thickness of the polishing pad after dressing when the polishing pad is dressed.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: July 17, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Toru Matsuzaki
  • Method of analyzing thermal stress according to filling factor of filler in resin
    Patent number: 8215829
    Abstract: A method of analyzing thermal stress includes calculating a distribution of the number of fillers in a composite integrally molded product by using physical property values of resin material containing fillers, and determining a coefficient of linear expansion of the resin material in the composite integrally molded product, that is used as an input condition of a thermal stress analysis, based on the distribution of the number of the fillers.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: July 10, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Tsutomu Kono, Masayuki Mino, Hidehiro Takeshima, Youkou Ito, Tomoko Goi
  • Semiconductor device that can adjust substrate voltage
    Patent number: 8217712
    Abstract: To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: July 10, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Shinichi Miyatake, Seiji Narui, Hitoshi Tanaka
  • Semiconductor device provided with wire that electrically connects printed wiring board and semiconductor chip each other
    Patent number: 8217517
    Abstract: In one embodiment, a semiconductor device includes a printed wiring board provided with a connection pad, a semiconductor chip provided with an electrode pad and a conductive wire. One end of the conductive wire is connected to the connection pad of the printed wiring board and the other end of the conductive wire is connected to the electrode pad of the semiconductor chip. The semiconductor chip is mounted on the printed wiring board so that the first surface of the semiconductor chip provided with the electrode pad is oriented opposite to the printed wiring board. A first insulating layer is formed on the first surface of the semiconductor chip oriented opposite to the printed wiring board. A thermoplastic second insulating layer is formed on the first insulating layer. Part of the conductive wire between one end and the other end is buried in the second insulating layer.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: July 10, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Keiyo Kusanagi
  • System with controller and memory
    Patent number: 8213258
    Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: July 3, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Atsuo Koshizuka
  • Semiconductor device
    Patent number: 8213246
    Abstract: A semiconductor device includes a test circuit that generates a pulse signal from a timing signal. The test circuit outputs the pulse signal and a first set of address signals in response to a first type transition of the timing signal. The test circuit outputs the pulse signal and a second set of address signals in response to a second type transition of the timing signal. The second set of address signals is different from the first set of address signals.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: July 3, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Jun Suzuki, Yasuhiro Matsumoto, Atsuko Momma
  • Apparatus including column having hollow part filled with filler and solid film-formation material
    Patent number: 8211229
    Abstract: A solid film-formation material feeding apparatus includes a supercritical fluid supply source for supplying supercritical fluid; and a column which is connected to the supercritical fluid supply source, and has a hollow part which is filled with a filler which is inactive for the supercritical fluid, wherein the hollow part can be further filled with a solid film-formation material which is soluble in the supercritical fluid. A column assembly which includes a plurality of the columns which may be connected in parallel to each other.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: July 3, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Ode
  • METHOD FOR FORMING NITRIDE FILM
    Publication number: 20120164848
    Abstract: A plasma-assisted ALD method using a vertical furnace and being performed by repeating a cycle until a desired film thickness is obtained is disclosed. The cycle comprises introducing a source gas containing a source to be nitrided, adsorbing, purging, introducing a nitriding gas and nitriding the source, and then, purging. A flow rate of a second carrier gas during introduction of the nitriding gas is reduced relative to that of a first carrier gas during introduction of the source gas. Particularly, a flow ratio of NH3 gas as the nitriding gas to N2 gas as the second carrier gas is 50:3 or less.
    Type: Application
    Filed: December 28, 2011
    Publication date: June 28, 2012
    Applicants: Tokyo Electron Limited, Elpida Memory, Inc.
    Inventors: Motoki FUJII, Masanobu MATSUNAGA, Kazuya YAMAMOTO, Kota UMEZAWA
  • Latency counter, semiconductor memory device including the same, and data processing system
    Patent number: 8208340
    Abstract: A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 26, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroki Fujisawa
  • Transmission system where a first device generates information for controlling transmission and latch timing for a second device
    Patent number: 8209560
    Abstract: To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and the data output circuit fetches data in response to multi-phase clock signals having different phases to be timing signals for fetching data, and adjusts a valid range for fetching data to be substantially uniform for each of the multi-phase clock signals. According to the present invention, the window width of data can be made uniform by individually adjusting the multi-phase clock signals that are input or output timing signals, and thus characteristics of the semiconductor device can be improved.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: June 26, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Toru Ishikawa
  • Semiconductor memory device that can relief defective address
    Patent number: 8208324
    Abstract: To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: June 26, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Noriaki Mochida, Kyoichi Nagata
  • Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit
    Patent number: RE43539
    Abstract: An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: July 24, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Tsugio Takahashi