Patents Assigned to .Engineering, Inc.
  • Package structure and method for manufacturing the same
    Patent number: 11894340
    Abstract: A package structure includes a wiring structure and a first electronic device. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The first electronic device is electrically connected to the wiring structure, and has a first surface, a second surface and at least one lateral side surface extending between the first surface and the second surface. The first electronic device includes a first active circuit region and a first protrusion portion. The first protrusion portion protrudes from the at least one lateral side surface of the first electronic device. A portion of the first active circuit region is disposed in the first protrusion portion.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Syu-Tang Liu, Min Lung Huang, Huang-Hsien Chang, Tsung-Tang Tsai, Ching-Ju Chen
  • PACKAGE STRUCTURE
    Publication number: 20240038698
    Abstract: A package structure is provided. The package structure includes a substrate, a conductive pad, and a conductive wire. The conductive pad is disposed over the substrate. The conductive wire includes an end portion connected to the conductive pad, wherein a grain arrangement of the end portion is distinct from a grain arrangement of the conductive pad.
    Type: Application
    Filed: June 6, 2023
    Publication date: February 1, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Erh-Ju LIN
  • ELECTRONIC DEVICES
    Publication number: 20240038679
    Abstract: The present disclosure provides an electronic device. The electronic device includes a first electronic component, a first conductive element, and a voltage regulator. The voltage regulator is disposed adjacent to the first electronic component. The voltage regulator is configured to regulate a first voltage from the first EMI shielding layer and to provide the first electronic component with a second voltage.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Nan LEE, Jung Jui KANG, Chang Chi LEE
  • ELECTRONIC DEVICE
    Publication number: 20240038678
    Abstract: The present disclosure provides an electronic device. The electronic device includes a first interposer, a first interconnection array, a first shielding wall, and a second interconnection array. The first interconnection array is disposed in the first interposer and electrically connected to ground. The first shielding wall continuously extends at a side of the first interconnection array. The second interconnection array is disposed between the first shielding wall and the first interconnection array. The second interconnection array is configured to transmit a signal.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin-Yu CHEN, Huei-Shyong CHO, Shih-Wen LU
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240038677
    Abstract: A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a protective element, and a sensor device. The protective element encapsulates the carrier. The sensor device is embedded in the carrier and the protective element. The sensor device includes a sensing portion and a protective portion adjacent to the sensing portion, and the protective portion of the sensor device has a first surface exposed from the protective element and the carrier.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ying-Chung CHEN, Lu-Ming LAI
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240038712
    Abstract: A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung Jui KANG, Shih-Yuan SUN, Chieh-Chen FU
  • Semiconductor devices, semiconductor device packages and method for manufacturing the same
    Patent number: 11887943
    Abstract: A capacitor structure includes a first metal layer, a first metal oxide layer, a second metal oxide layer, a first conductive member, a second conductive member and a metal composite structure. The first metal layer has a first surface and a second surface opposite the first surface. The first metal oxide layer is formed on the first surface of the first metal layer. The second metal oxide layer is formed on the second surface of the first metal layer. The first conductive member penetrates through the capacitor structure and is electrically isolated from the first metal layer. The second conductive member is electrically connected to the first metal layer. The metal composite structure is disposed between the second conductive member and the first metal layer.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Recessed portion in a substrate and method of forming the same
    Patent number: 11886015
    Abstract: A recessed portion in a semiconductor substrate and a method of forming the same are provided. The method comprises: forming a mask on the semiconductor substrate; forming a protection layer on a top surface of the mask and on at least one sidewall of the mask, and on at least one surface of the semiconductor substrate exposed by the mask; performing a first etching process to remove the protection layer on the top surface of the mask and on a bottom surface of the semiconductor substrate exposed by the mask; and performing a second etching process to remove the remaining protection layer and to etch the semiconductor substrate to form the recessed portion. In this way, a recessed portion with relatively smooth and vertical sidewalls can be realized.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao Hsuan Chuang, Huang-Hsien Chang
  • Electronic package and method of manufacturing the same
    Patent number: 11888210
    Abstract: The present disclosure provides an electronic package. The electronic package includes an antenna structure having a first antenna and a second antenna at least partially covered by the first antenna. The electronic package also includes a directing element covering the antenna structure. The directing element has a first portion configured to direct a first electromagnetic wave having a first frequency to transmit via the first antenna and a second portion configured to direct a second electromagnetic wave having a second frequency different from the first frequency to transmit via the second antenna. A method of manufacturing an electronic package is also provided.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jenchun Chen, Ya-Wen Liao
  • Semiconductor device package
    Patent number: 11888081
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Yi Wu, Chang Chin Tsai, Bo-Yu Huang, Ying-Chung Chen
  • Package structure with interposer encapsulated by an encapsulant
    Patent number: 11887928
    Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Sheng-Wen Yang, Teck-Chong Lee, Yen-Liang Huang
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11887967
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed by the first package body.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shang-Ruei Wu, Chien-Yuan Tseng, Meng-Jen Wang, Chen-Tsung Chang, Chih-Fang Wang, Cheng-Han Li, Chien-Hao Chen, An-Chi Tsao, Per-Ju Chao
  • System and method for manufacturing a semiconductor package structure
    Patent number: 11887865
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) measuring an amount of a molding powder; (b) controlling the amount of a molding powder; and (c) dispensing the molding powder on an assembly structure including a carrier and at least one semiconductor device disposed on the carrier.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chenghan She
  • ELECTRONIC DEVICE
    Publication number: 20240030135
    Abstract: An electronic device is disclosed. The electronic device includes a carrier including a first region and a second region distinct from the first region. The electronic device also includes an electronic component covering the first region and at least partially exposing the second region. The electronic device also includes a first power regulating element in the second region of the carrier and a second power regulating element. The second power regulating element is disposed adjacent to the first power regulating element and electrically connected to the electronic component through the first power regulating element to provide a first power path.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Nan LEE, Jung Jui KANG, Chang Chi LEE
  • ELECTRONIC DEVICE
    Publication number: 20240030125
    Abstract: An electronic device is disclosed. The electronic device includes a first circuit structure, a first die, a second die, and a third die. The first die is disposed below the first circuit structure. The second die is disposed below the first circuit structure. The third die is disposed above the first circuit structure and electrically connects the first die to the second die. The first die communicates with the second die through the third die.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung Jui KANG, Chang Chi LEE
  • SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240030120
    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE
  • Embedded component package structure and manufacturing method thereof
    Patent number: 11882660
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: January 23, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Chien-Hao Wang
  • Semiconductor package structure having substrate with embedded electronic component and conductive pillars
    Patent number: 11881448
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first package and a second package. The first package includes a first substrate, an electronic component, a trace layer, and a first conductive structure. The first substrate has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the first substrate. The trace layer has an uppermost conductive layer embedded in the first substrate and exposed from the first surface of the first substrate. The first conductive structure electrically connects the trace layer to the second surface of the first substrate. The second package is disposed on the first surface of the first substrate of the first package.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: January 23, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt, Kay Stefan Essig
  • ELECTRONIC DEVICE
    Publication number: 20240023239
    Abstract: An electronic device is disclosed. The electronic device includes a carrier, a computing element disposed over the carrier, and a first data storage element disposed over the carrier and electrically connected with the computing element through the carrier. The computing element is configured to receive a first power provided from the first data storage element.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung Jui KANG, Chang Chi LEE
  • Ladder platform with stairs
    Patent number: D1013899
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: February 6, 2024
    Assignee: NSAFE Engineering, Inc.
    Inventors: Chester J. Budziak, Adam P. Budziak, Gregory C. Budziak