Patents Assigned to .Engineering, Inc.
  • Publication number: 20240062135
    Abstract: The present invention relates to a control method for a control apparatus for an aircraft, the control apparatus including a communication unit and a processor. The control method includes receiving an address of a delivery location to which a delivery product is to be delivered, and controlling an aircraft by means of the communication unit to deliver the delivery product to the delivery location, in which the controlling of the aircraft by means of the communication unit includes selecting, on the basis of the address, any one of a plurality of delivery criteria that defines an area into which the aircraft is to unload the delivery product, establishing a delivery area and a flight lane to the delivery area on the basis of the delivery criterion, controlling the aircraft to allow the aircraft to fly along the flight lane, and controlling the aircraft to unload the delivery product into the delivery area when the aircraft reaches the delivery area.
    Type: Application
    Filed: November 17, 2021
    Publication date: February 22, 2024
    Applicant: THIS IS ENGINEERING INC.
    Inventor: Yoo Jung HONG
  • Publication number: 20240063163
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Ming-Chi LIU, Yu-Ting LU, Kai-Chiang HSU, Che-Ting LIU
  • Publication number: 20240063159
    Abstract: A package structure is disclosed. The package structure includes a substrate including a conductive element and a plurality of wires having a surface area through which heat of the conductive element can be dissipated, lowering a bonding temperature of the conductive element. The package structure also includes a conductive layer disposed between the conductive element of the substrate and the plurality of wires. The conductive contact layer attaches the plurality of wires over the conductive element.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Chin-Li KAO
  • Patent number: 11908815
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11908786
    Abstract: A wiring structure includes a test pattern layer. The test pattern layer includes a test circuit pattern and a heat dissipating structure. The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ting Wei Hsu
  • Patent number: 11908781
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chih Cho, Chun-Hung Yeh, Tsung-Wei Lu
  • Patent number: 11906394
    Abstract: There is described a method of locating an area of interest in a conduit, comprising: measuring multiple acoustic signals at multiple locations along the conduit; for each acoustic signal, determining its autocorrelation; and applying a relationship to the determined autocorrelations to estimate a location of the area of interest, wherein the relationship is between autocorrelations of acoustic signals measured in a modelled conduit and modelled areas of interest in the modelled conduit, wherein it is assumed that acoustic signals propagating along the modelled conduit reflect from at least one point in the modelled conduit.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: February 20, 2024
    Assignee: HIFI ENGINEERING INC.
    Inventors: Arne Dankers, Seyed Ehsan Jalilian
  • Publication number: 20240055365
    Abstract: An electronic device is disclosed. The electronic device includes a first interconnection structure, and a first electronic component disposed over the first interconnection structure and having an active surface and a lateral surface. The electronic device also includes a power connection disposed between the first interconnection structure and the active surface of the first electronic component, and a first non-power connection extending along the lateral surface of the first electronic component and electrically connected to the first interconnection structure. The electronic device also includes a second non-power connection disposed between the first interconnection structure and the active surface of the first electronic component. The second non-power connection is configured to block an electromagnetic interference (EMI) between the power connection and the first non-power connection.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-I WU, Jung Jui KANG, Chang Chi LEE, Pao-Nan LEE, Ming-Fong JHONG
  • Patent number: 11901270
    Abstract: A semiconductor device package includes a substrate and a conductive lid. The conductive lid is disposed within the substrate. The conductive lid defines a waveguide having a cavity. The waveguide is configured to transmit a signal from a first electronic component to a second electronic component through the cavity.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: February 13, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Shih-Wen Lu
  • Patent number: 11900301
    Abstract: An information processing device is configured to output work information related to work performed by a serving person, the information processing device including an image acquisition unit configured to acquire an original image including a served person and a plurality of served objects that the serving person serves, an image division unit configured to divide the original image into a served-person image, in which the served person is captured, and a plurality of served-object images, in which each served object is captured, a scene estimation unit configured to estimate a scene, which is the situation the serving person is in, by using a first trained model, a chunk estimation unit configured to estimate a chunk, which is information dividing or suggesting the work information, by using one of a plurality of second trained models, and an output unit configured to output the chunk.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: February 13, 2024
    Assignee: INFORMATION SYSTEM ENGINEERING INC.
    Inventor: Satoshi Kuroda
  • Patent number: 11901252
    Abstract: A semiconductor device package includes a first substrate, a second substrate, and a first electronic component between the first substrate and the second substrate. The first electronic component has a first surface facing the first substrate and a second surface facing the second substrate. The semiconductor device package also includes a first electrical contact disposed on the first surface of the first electronic component and electrically connecting the first surface of the first electronic component with the first substrate. The semiconductor device package also includes a second electrical contact disposed on the second surface of the first electronic component and electrically connecting the second surface of the first electronic component with the second substrate. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 13, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Han Wang, Ian Hu
  • Patent number: 11901245
    Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: February 13, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chen-Chao Wang, Chih-Yi Huang, Keng-Tuan Chang
  • Publication number: 20240043222
    Abstract: This disclosure provides a conveyor system having a track bogie with a pair of continuous tracks. A conveyor chassis is rotatably connected with the track bogie. A pivotal king pin is positioned between the continuous tracks and operable for pivoting between a raised position and a lowered tow position, the raised position allowing for operation of the continuous tracks on a ground surface and the lowered tow position allowing for connection with a tow vehicle.
    Type: Application
    Filed: June 23, 2023
    Publication date: February 8, 2024
    Applicant: MGL Engineering Inc.
    Inventor: GARY LOVE
  • Patent number: 11892570
    Abstract: An optical assembly includes a light-emitting device, a partition structure and a cover. The partition structure defines a first space for accommodating the light-emitting device. The cover is disposed over the partition structure. The cover has a first surface facing the partition structure and a second surface opposite to the first surface. A light emitted by the light-emitting device forms a first irradiance pattern projected on the second surface of the cover, and the first irradiance pattern includes a first dark zone traversing the first irradiance pattern.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsin-Ying Ho
  • Patent number: 11894354
    Abstract: An optoelectronic device package includes a first redistribution layer (RDL), a first electronic die disposed over the first RDL, wherein an active surface of the first electronic die faces the first RDL. The optoelectronic device package further includes a second electronic die disposed over the first RDL, and a photonic die disposed over and electrically connected to the second electronic die. An active surface of the second electronic die is opposite to the first RDL.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chi-Han Chen
  • Patent number: 11894308
    Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Ming Wang, Tien-Szu Chen, Wen-Chih Shen, Hsing-Wen Lee, Hsiang-Ming Feng
  • Patent number: 11894317
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-Hsien Ke, Teck-Chong Lee, Chih-Pin Hung
  • Patent number: 11891155
    Abstract: A bicycle front derailleur is provided, including: a base, configured to be mounted to a bicycle frame; a linkage mechanism, including a connection portion configured to be connected with a cable, the linkage mechanism being swingably connected to the base; a chain guide, swingably connected to the linkage mechanism; and an adjustment assembly, disposed on the base, including a holder movably disposed on the base and an adjustment member, the holder being configured to be connected with a sheath for driving the cable, the adjustment member being movably disposed on the base and adjustable to drive the holder to move relative to the base.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: February 6, 2024
    Assignee: AD-II ENGINEERING INC.
    Inventors: Kai-Hung Hu, Yu-Hsuan Cheng
  • Patent number: 11894293
    Abstract: A circuit structure and an electronic structure are provided. The circuit structure includes a low-density conductive structure, a high-density conductive structure and an electrical connection structure. The high-density conductive structure is disposed on the low-density conductive structure. The electrical connection structure extends through the high-density conductive structure and is electrically connected to the low-density conductive structure. The electrical connection structure includes a shoulder portion.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11892346
    Abstract: An optical system and a method of manufacturing an optical system are provided. The optical system includes a carrier, a light emitter, a light receiver, a block structure and an encapsulant. The light emitter is disposed on the carrier. The light receiver is disposed on the carrier and physically spaced apart from the light emitter. The light receiver has a light detecting area. The block structure is disposed on the carrier. The encapsulant is disposed on the carrier and covers the light emitter, the light receiver and the block structure. The encapsulant has a recess over the block structure.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsin-Ying Ho, Ying-Chung Chen