Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a first P-type semiconductor layer is provided, and an N-type semiconductor layer and a second P-type semiconductor layer are formed in sequence on the first P-type semiconductor layer. The first P-type semiconductor layer, the N-type semiconductor layer and the second P-type semiconductor layer all include a GaN-based material. When the first P-type semiconductor layer is provided, its upper surface is controlled to be a Ga surface; when the N-type semiconductor layer is formed, its upper surface is controlled to be an N surface; when the second P-type semiconductor layer is formed, its upper surface is controlled to be an N surface.

Abstract: The present disclosure provides a semiconductor structure and substrate thereof, and manufacturing methods for semiconductor structure and substrate thereof. In the method for manufacturing the substrate, at least one of groove is provided in each subunit region on a surface of a premanufactured substrate, and the premanufactured substrate includes at least one unit region, each of the at least one unit region includes at least two subunit regions, the at least one of groove is filled with heat conduction materials to form a substrate; in one of the at least one unit region, the at least two subunit regions respectively have different heat conduction coefficients.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first n-type semiconductor layer, a p-type semiconductor layer, and a second n-type semiconductor layer which are stacked. A buried layer made of AlGaN is disposed in the first n-type semiconductor layer. A trench at least penetrates through the second n-type semiconductor layer and the p-type semiconductor layer. At least part of the buried layer is reserved below the trench. A gate electrode is in the trench. The method is used to manufacture this semiconductor structure.

Abstract: The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming an amorphous layer on the substrate, wherein the amorphous layer includes a plurality of patterns to expose part of the substrate; forming a metal nitride layer on the amorphous layer; removing the amorphous layer to form a plurality of cavities between the substrate and the metal nitride layer; removing the substrate to form the semiconductor structure. In the present invention, an amorphous layer is formed on the substrate, and a metal nitride layer is formed on the amorphous layer. The amorphous layer can inhibit slip or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer and improving the performance of the semiconductor structure, while the metal nitride layer can realize self-supporting.

Abstract: Disclosed is a graphite plate to solve a problem of poor performance uniformity of an epitaxial wafer obtained by using a graphite plate for epitaxial growth. The graphite plate includes a graphite plate body, the graphite plate body includes a carrying recess, and at least part of the inner wall of the carrying recess is covered with a heat insulation material.

Abstract: Disclosed is a graphite plate to solve a problem of poor performance uniformity of an epitaxial wafer obtained during carrying on epitaxial growth of material using the graphite plate. A graphite plate includes: a graphite plate body, includes a carrying recess and a recess located on one side of the carrying recess away from a central point of the graphite plate body; and a stopper, which is embedded in the recess in a matching manner, and the stopper protrudes from the bottom surface of the carrying recess to form a limiting structure.

Abstract: A preparation method for a resonant cavity light-emitting diode comprises: forming a first mirror and a first semiconductor layer on a substrate in sequence; forming an active layer on the first semiconductor layer; and forming a second semiconductor layer and a second mirror on the active layer in sequence. The preparation method further comprises: planarizing at least one of a first contact surface between the first semiconductor layer and the first mirror, and a second contact surface between the second semiconductor layer and the second mirror. Since the first contact surface between the first semiconductor layer and the first mirror, and/or the second contact surface between the second semiconductor layer and the second mirror is planarized, the light emission uniformity of the resonant cavity light-emitting diode can be improved.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate on which at least one light guide groove is provided, the light guide groove penetrating the substrate; and a light emitting structure disposed on one side of the substrate, the light emitting structure including at least one set of a first electrode and a second electrode. The light guide groove at least corresponds to one set of a first electrode and a second electrode to prevent bad points. A wavelength conversion dielectric layer is filled into the light guide groove to avoid a coffee ring effect and achieve uniform and full-color light emission of a light emitting device. The semiconductor structure may further save manufacturing costs and prevent crosstalk between light emitted from various light emitting units.

Abstract: The present disclosure provides a semiconductor structure and substrate thereof, and a method for manufacturing the same. In the method for manufacturing the substrate, at least one of groove is provided in each unit sub-region on a surface of a premanufactured substrate, and the premanufactured substrate includes at least one unit region, each of the at least one unit region includes at least two unit sub-regions; in one of the at least one unit region, the at least two unit sub-regions respectively have different porosities, the premanufactured substrate is annealed to form a substrate, wherein openings of the grooves are healed to form self-healing layers, and the grooves that are not fully healed form gaps. When a susceptor transfers heat to the substrate, the unit sub-regions with different porosities respectively have different heat conduction efficiencies.

Abstract: Disclosed is an enhancement-mode semiconductor device, comprising: a substrate; a p-type nitride semiconductor layer and an n-type nitride semiconductor layer formed on the substrate in sequence, the p-type nitride semiconductor layer having a first protruding structure at a gate region of the p-type nitride semiconductor layer; the n-type nitride semiconductor layer having a first through hole corresponding to the first protruding structure, exposing the gate region of the p-type nitride semiconductor layer; a channel layer conformally disposed on the n-type semiconductor layer and the first protruding structure; a barrier layer, the barrier layer being conformally disposed on the channel layer. The enhancement-mode semiconductor device has a simple structure, a good repeatability, and avoids impurities and defects brought to the channel layer and the barrier layer.

Abstract: Disclosed is an enhancement-mode semiconductor device, comprising: a substrate; a p-type semiconductor layer, the p-type semiconductor layer being disposed on the substrate; an n-type semiconductor layer, the n-type semiconductor layer being disposed on the p-type semiconductor layer, a groove being formed in a gate region of the n-type semiconductor layer, and the first groove penetrating the n-type semiconductor layer; a channel layer, the channel layer being conformally disposed on the n-type semiconductor layer and in the first groove; and a barrier layer, the barrier layer being conformally disposed on the channel layer. The enhancement-mode semiconductor device has a simple structure, a good repeatability, and avoids bringing impurities and defects to the channel layer and the barrier layer.

Abstract: A semiconductor structure includes a substrate; a nucleation layer located above the substrate; and a metal nitride thin film located between the nucleation layer and the substrate. A diffusion of atoms in a material of the substrate is suppressed by depositing the metal nitride thin film between the substrate and the nucleation layer, so that a thickness of the nucleation layer is significantly reduced, and a total thermal resistance of the semiconductor structure is reduced.

Abstract: Disclosed are a light-emitting device, a template of the light-emitting device and preparation methods thereof. The template of the light-emitting device comprises a substrate; a GaN-based semiconductor layer and a mask layer provided on the substrate, where the mask layer comprises a plurality of mask openings provided at intervals, and the plurality of mask openings are filled with the GaN-based semiconductor layer; and a sacrificial layer provided on a surface of the GaN-based semiconductor layer away from the substrate and located in the plurality of mask openings provided at intervals.

Abstract: The present application provides methods for manufacturing a vertical device. To begin with, a GaN-based semiconductor substrate (10) is etched from a front surface (10a) to form a trench (101). Then, a P-type semiconductor layer (11) and an N-type semiconductor layer (12) are sequentially formed on a bottom wall and side walls of the trench (101) and the front surface (10a) of the semiconductor substrate. The trench (101) is partially filled with the P-type semiconductor layer (11). Thereafter, the N-type semiconductor layer (12) and the P-type semiconductor layer (11) are planarized, and the P-type semiconductor layer (11) and the N-type semiconductor layer (12) in the trench (101) are retained. Next, a gate structure (13) is formed at a gate area of the front surface (10a) of the semiconductor substrate, a source electrode (14) is formed on two sides of the gate structure (13), and a drain electrode (15) is formed on a rear surface (10b) of the semiconductor substrate respectively.

Abstract: A surface roughening method includes the following steps: preparing a first epitaxial layer of a three-dimensional island shape growth over a light emitting structure; and preparing a discontinuous second epitaxial layer over the first epitaxial layer. The surface roughening method provided in the present application is simple and convenient, and improves the efficiency. In addition to the epitaxial growth process, it is not necessary to use an additional process such as wet etching, photonic crystal and other processes to further process the surface of the epitaxial layer, and the method may be implemented by means of one process in a same reaction equipment.

Abstract: An enhancement-mode device includes: a substrate; a channel layer and a barrier layer successively formed on the substrate; an n-type semiconductor layer formed on the barrier layer, a gate region being defined on a surface of the n-type semiconductor layer; a groove that is formed in the gate region and at least partially runs through the n-type semiconductor layer; and a p-type conductor material that is formed on the surface of the n-type semiconductor layer and at least fills the inside of the groove.

Abstract: A nitride power transistor comprises: a silicon substrate comprising a differently doped semiconductor composite structure for forming a space charge depletion region; and a nitride epitaxial layer located on the silicon substrate. With introduction of a differently doped semiconductor composite structure for forming a space charge depletion region inside a silicon substrate of a nitride power transistor, the nitride power transistor is capable of withstanding a relatively high external voltage, and thus a breakdown voltage of the device is improved.

Abstract: An patterned Si substrate-based LED epitaxial wafer and a preparation method therefor, the LED epitaxial wafer comprising: a patterned Si substrate (1) and an Al2O3 coating (2) growing on the patterned Si substrate (1); sequentially growing on the Al2O3 coating (2) are a nucleating layer (3), a first buffer layer (4), a first insertion layer (5), a second buffer layer (6), a second insertion layer (7), an n-GaN layer (8), a quantum well layer (9), a p-GaN layer (10), an n-electrode (14) electrically connected to the n-GaN layer and a p-electrode (13) electrically connected to the p-GaN layer. The present invention is suitable for the preparation of large-sized LED epitaxial wafers. Furthermore, the crystal quality is improved, and the light extraction efficiency of the LED die is improved.

Abstract: A method for preparing a p-type semiconductor layer, an enhanced device and a method for manufacturing the same disclosed relate to the technical field of microelectronics. The method for preparing a p-type semiconductor layer includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a substrate with a first melting point. A sacrificial layer with a second melting point is forming over the substrate. The second melting point is less than the first melting point. A stack of semiconductor layers is formed over the sacrificial layer. The stack of semiconductor layers has a third melting point greater than the second melting point and a formation temperature less than the second melting point. A thermal process is performed at a temperature greater than the second melting point and less than the first melting point and the third melting point in order to melt the sacrificial layer such that the substrate is stripped from the stack of semiconductor layers.