Abstract: The present disclosure provides a GaN-based semiconductor structure, including: a substrate; a channel layer; a barrier layer, where the channel layer and the barrier layer each include a gate region, a source region and a drain region; a source region N-type ion heavily-doped layer located in the source region; a drain region N-type ion heavily-doped layer located in the drain region; a gate electrode located in the gate region; a source electrode located on the source region N-type ion heavily-doped layer; and a drain electrode located on the drain region N-type ion heavily-doped layer.

Abstract: The present disclosure provides a GaN-based semiconductor structure, including: a substrate; a channel layer; a barrier layer, where the channel layer and the barrier layer each include a channel region, a source region and a drain region; one or more grooves provided in at least one of the source region or the drain region, where, for each of the grooves, a length of a first side edge adjacent to the channel region and located on a bottom wall of the groove is larger than a length of an orthographic projection of the first side edge on a vertical plane in a length direction of the channel region; a source region N-type ion heavily-doped layer and a drain region N-type ion heavily-doped layer; and a gate electrode, a source electrode, and a drain electrode.

Abstract: Disclosed is a full-color LED epitaxial structure, having different area ratios of pillars corresponding to an unit area of a substrate, which is utilized to realize different flow rates of reaction gas around each of the pillars when a light-emitting layer is grown, and different doping efficiency of each element in the growing light-emitting layer, which in turn realizes different composition ratios of each element in the growing light-emitting layer and different light-emitting wavelengths of LED. The above process is simple and the full-color LED semiconductor structure can be produced on a single substrate. And light-emitting wavelengths of LED can be adjusted only by adjusting the area ratio of the pillars to adjust a composition ratio of the light-emitting layer, thus reducing manufacturing processes of the full-color LED.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the semiconductor structure, a semiconductor substrate, a heterojunction and an in-situ insulation layer are disposed from bottom to top, a trench is provided in the in-situ insulation layer, and a transition layer is located on at least an in-situ insulation layer, the p-type semiconductor layer is located in the trench and on the gate region of the transition layer, and the heavily doped n-type layer is located on at least one of the p-type semiconductor layer in the gate region, the source region of the heterojunction, or the drain region of the heterojunction.

Abstract: Disclosed is a preparation method for a semiconductor structure. The semiconductor structure includes: a substrate; an epitaxial layer and an epitaxial structure that are stacked on the substrate in sequence. The epitaxial layer is doped with a doping element. In the forming process, a sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that a concentration of the doping element in the epitaxial layer is lower than a preset value. In this application, the sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that the concentration of the doping element in the epitaxial layer is lower than the preset value, so as to prevent the doping element in the epitaxial layer from being precipitated upward into an upper-layer structure, ensure the mobility of electrons in a channel layer, and improve the performance of a device.

Abstract: Provided are a semi-conductor structure and a manufacturing method thereof. The semi-conductor structure includes: a substrate, a heterojunction, a P-type ion doped layer and a gate insulation layer disposed from bottom to top, wherein the heterojunction includes a source region, a drain region and a gate region; the P-type ion doped layer in the gate region includes an activated region and non-activated regions, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated regions are passivated; the non-activated regions include at least two regions which are spaced apart in a direction perpendicular to a connection line of the source region and the drain region; the gate insulation layer is located on the non-activated region to expose the activated region.

Abstract: This application provides semiconductor structures and methods of manufacturing the same. A semiconductor structure includes: an N-type semiconductor layer, a light emitting layer, and a P-type ion doped layer that are disposed from bottom to up, wherein the P-type ion doped layer comprises an activated region and non-activated regions located on two sides of the activated region, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated region are passivated. The layout of the activated region and the non-activated regions makes an LED include: a high-efficiency light emitting region and light emitting obstacle regions located on two sides of the high-efficiency light emitting region.

Abstract: Provided is a method of manufacturing a semiconductor structure. The method includes: providing a substrate, where the substrate includes a plurality of component areas and peripheral areas surrounding the plurality of component areas; next, forming a sacrificial layer on each of the plurality of component areas, and forming a semiconductor active layer on the sacrificial layer and the substrate not covered with the sacrificial layer; patterning the semiconductor active layer to remove the semiconductor active layer on the peripheral areas so as to form a plurality of annular grooves which expose the sacrificial layer, such that the semiconductor active layer on each of the plurality of component areas is independent; afterwards, removing the sacrificial layer on each of the plurality of component areas through the annular grooves, such that the independent semiconductor active layer is separated from the substrate, where the independent semiconductor active layer forms a semiconductor structure.

Abstract: Disclosed are an optoelectronic device and a preparation method thereof. The optoelectronic device includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence. The conductivity type of the first semiconductor layer is opposite to that of the second semiconductor layer, and the second semiconductor layer is provided with a layer of nano-diamond structure, and the nano-diamond structure has the same conductivity type as the second semiconductor layer. The method for preparing the optoelectronic device is used to make the optoelectronic device. In the present application, by providing a layer of nano-diamond structure in the second semiconductor layer, the absorption of UV light emitted by the active layer can be effectively avoided, and the beneficial effect of greatly improving the light extraction efficiency of the UV LED can be achieved.

Abstract: Provided are a Schottky diode and a manufacturing method therefor.

Abstract: Provided are a diode and a manufacturing method therefor. The diode includes: a nitride channel layer; a nitride barrier layer, formed on the nitride channel layer; an oxidation forming layer, wherein a part of the oxidation forming layer is positioned in the nitride barrier layer, and a surface of the oxidation forming layer away from the nitride channel layer is flush with a surface of the nitride barrier layer away from the nitride channel layer; a passivation layer, formed on the nitride barrier layer, wherein the passivation layer includes a first groove penetrating through the passivation layer to expose the oxidation forming layer and a part of the nitride barrier layer; and a first electrode, formed in the first groove, wherein the first electrode is in contact with the nitride barrier layer and the oxidation forming layer.

Abstract: The present disclosure provides a method for manufacturing vertical device. The method includes: forming a plurality of first grooves in the front side of the N-type heavily doped layer; forming an N-type lightly doped layer in the plurality of first grooves and on the front side of the N-type heavily doped layer; forming second grooves in the N-type lightly doped layer; forming a P-type semiconductor layer in the second grooves and on the front side of the N-type lightly doped layer; planarizing the P-type semiconductor layer; forming a passivation layer on the planarized structure; forming a third groove in the passivation layer, wherein the third groove has a depth equal to a thickness of the passivation layer; and forming a first electrode and a second electrode.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate, a heterojunction structure, a cap layer, a first passivation layer and a second passivation layer disposed from bottom to up; a trench penetrating through the first passivation layer and the second passivation layer; and a P-type semiconductor layer located at least on an inner wall of the trench. After a part of the second passivation layer is dry etched to form the trench, the first passivation layer can be used for etching endpoint detection to avoid over etching. A part of the first passivation layer exposed by the trench of the second passivation layer can be removed by wet etching. When the exposed part of the first passivation layer is removed by the wet etching, due to the cap layer has extremely high stability, after the exposed part of the first passivation layer is removed by the wet etching, the cap layer will not be damaged.

Abstract: Embodiments of the present application provide a semiconductor structure and a manufacturing method therefor. A buffer layer is disposed on a substrate layer, and the buffer layer includes a first buffer layer and a second buffer layer. By doping a transition metal in the first buffer layer, a deep level trap may be formed to capture background electrons, and diffusion of free electrons toward the substrate may also be avoided. By decreasing a doping concentration of the transition metal in the second buffer layer, a tailing effect is avoided and current collapse is prevented. By doping periodically the impurity in the buffer layer, the impurity may be as an acceptor impurity to compensate the background electrons, and then a concentration of the background electrons is reduced. By using the periodic doping method, dislocations, caused by doping, in the buffer layer may be effectively reduced.

Abstract: The present application provides a semiconductor structure. The semiconductor structure includes a channel layer and a barrier layer provided on the channel layer. The barrier layer includes multiple barrier layers arranged in a stack, the multiple barrier sub-layers include at least three barrier sub-layers, and Al component proportions of the multiple barrier sub-layers vary along a growth direction of the barrier layer for at least one up-and-down fluctuation.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a P-type semiconductor layer is provided, where the P-type semiconductor layer includes a GaN-based material and an upper surface of the P-type semiconductor layer is a Ga surface. A first N-type semiconductor layer is formed on the P-type semiconductor layer, where the first N-type semiconductor layer comprises a GaN-based material. An upper surface of the first N-type semiconductor layer is an N surface. A part of the first N-type semiconductor layer is removed by wet etching to expose a part of the P-type semiconductor layer.

Abstract: Disclosed are a patterned substrate, a semiconductor device and a nanotube structure. The patterned substrate includes, in a vertical direction, a base plate and an AlN layer that are sequentially stacked. The patterned substrate includes, in the vertical direction, a first surface and a second surface that are oppositely arranged, a bottom surface of the base plate is the first surface of the patterned substrate, the second surface of the patterned substrate is a patterned surface, the second surface is provided with a plurality of grooves that are independent of each other in a horizontal direction and are arranged in an array, and at least part of the base plate is left below each of the plurality of grooves. According to the patterned substrate in the present application, a structure of the AlN layer is changed, so that an epitaxial structure grown subsequently is prevented from warping.

Abstract: The present invention provides a semiconductor structure and a preparation method thereof. A transition metal and an impurity are co-doped on a buffer layer above a substrate layer to reduce the leakage current of a semiconductor device, to improve the pinch-off behavior, and to avoid the device current collapse, moreover, the ranges of the concentration of the transition metal and the impurity in the buffer layer are controlled to ensure the balance of the leakage current during the dynamic characteristics of the device.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a channel layer, a barrier layer located on the channel layer, a composition change layer located on the barrier layer, and a p-type semiconductor material layer located in the gate region of the composition change layer, wherein a gate region is defined on a surface of the composition change layer, and a material of the composition change layer includes at least one composition change element.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a channel layer and a barrier layer that are sequentially superimposed, and a gate region being defined on a surface of the barrier layer; and a p-type semiconductor material layer formed in the gate region, the p-type semiconductor material layer including at least one composition change element, and a component of the composition change element changing along an epitaxial direction.