Abstract: A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.

Abstract: A signal processing device comprising at least one control unit arranged to receive at least one bit-expand instruction, decode the received at least one bit-expand instruction, and output at least one control signal in accordance with the received at least one bit-expand instruction. The signal processing device further includes at least one execution unit component arranged to receive at least one source register value comprising at least one data bit to be expanded, extract at least one data bit from the at least one source register value located at an offset position according to the at least one control signal, expand the at least one extracted data bit into at least one multi-bit data type, and output the at least one multi-bit data type to at least one destination register.

Abstract: An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.

Abstract: A method of operating a data processing system comprises: processing data words and switching between contexts; assigning a context signature Sig to any pair formed of a data word and a context; reading, within a current context, a data record from a memory unit, the data record comprising a payload data word and a protection signature; providing, as a verification signature, the context signature Sig of the payload data word and the current context; checking the verification signature against the protection signature; and generating an error signal if the verification signature differs from the protection signature.

Abstract: A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.

Abstract: The invention relates to a buffer circuit for a receiver device including a transconductance stage and an output stage coupled in parallel to output stages of other channels of the device. The output of the transconductance stage is connected to a base of a bipolar transistor in the output stage. A switch is connected between the base of the bipolar transistor and the emitter of the bipolar transistor. A controller is arranged to switch the buffer circuit from a switch-off mode to a switch-on mode and back. In switch-off mode the switch is switched on, so as to connect the base and the emitter of the bipolar transistor.

Abstract: A method of designing an integrated circuit is described. The integrated circuit comprises a plurality of circuit components, including one or more functional components and one or more tile shapes. A pcell instance may be defined to specify a functional component along with one or more tile shapes. The tile shapes are thus associated with the functional component. A netlist may be arranged to specify interconnections between the functional components of the integrated circuit as well as electrical interactions between the tile shapes and functional components. A computer program product for carrying out the method is also described.

Abstract: The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.

Abstract: A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period.

Abstract: In an operation scheduler adapted to schedule in an asynchronous contention-based system a first FIFO queue is adapted to store one trigger message or one operation request. A message router is coupled to the first FIFO queue and is adapted to route instructions to a second FIFO queue or a memory and locate in the memory the instructions of a suspended operation associated with a trigger message and authorise execution of the suspended operation. An arbitration unit is coupled to the second FIFO queue and to the memory, and is adapted to schedule the execution of instructions associated with a standalone non-preemptable operation during a period of time within which at least one operation of the first sequence is being suspended.

Abstract: An inertial sensor (110) includes a drive system (118) configured to oscillate a drive mass (114) within a plane (24) that is substantially parallel to a surface (50) of a substrate (28). The drive system (118) includes first and second drive units (120, 122) having fixed fingers (134, 136) interleaved with movable fingers (130, 132) of the drive mass (114). At least one of the drive units (120) is located on each side (126, 128) of the drive mass (114). Likewise, at least one of the drive units (122) is located on each side (126, 128) of the drive mass (114). The drive units (122) are driven in phase opposition to the drive units (120) so that a levitation force (104) generated by the drive units (122) compensates for, or at least partially suppresses, a levitation force (100) generated by the drive units (120).

Abstract: An apparatus for voltage ripple reduction on a power supply line of an integrated circuit device is provided to be operable in at least two modes. The apparatus includes: one or more clamping devices connectable to the power supply line; a clamp control unit; and a mode change detection unit arranged to monitor an interface of the integrated circuit device for one or more information indicating an upcoming mode change of the integrated circuit device and to provide a mode change signal to the clamp control unit when the one or more information is detected. The clamp control unit is arranged to connect at least one of the one or more clamping devices to the power supply line when receiving the mode change signal.

Abstract: In a system on chip responder units comprise one or more responder elements and is associated with one or more protection units. A request analysis unit is arranged to receive from a requesting requestor unit a request for access to one or more target responder elements among responder elements within a target responder unit among the responder units. The request analysis unit determines relevant protection data based on the request and an authorization list, which comprises one or more entries For each entry of the authorization list: taking access requirements specified by the respective entry into account if one or more of the target responder elements are part of the group of responder elements specified by the respective entry. The request analysis unit provides the relevant protection data to one or more target protection unit(s) associated with the responder unit(s), and located in a hierarchical path between the requesting requestor unit requestor unit and the target responder unit.

Abstract: A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.

Abstract: Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.

Abstract: A buck converter has an output node and a ground node, wherein a load is connected between the output node and the ground node and is arranged to drive an output current I_out through the output node, generating an output voltage V_out. A current control unit arranged to control the output current I_out in dependence on a control voltage V_ctl provided at a control node; and a voltage control unit arranged to provide the control voltage V_ctl. The voltage control unit comprises: an integrator unit arranged to control the control voltage V_ctl in dependence on a time integral of a difference between the output voltage and the reference voltage; at least one of an overshoot detector arranged to detect an overshoot of the output voltage V_out, and an undershoot detector arranged to detect an undershoot of the output voltage V_out.

Abstract: A phase detector for generating a phase difference signal indicative of a phase difference between a first bi-level signal of frequency F1 and a second bi-level signal of frequency F2 is proposed. The phase detector may include first and second detector inputs first and second flip-flops, a NAND gate, and a first and second overphase detection units. An output of the first overphase detection unit may be connected to a direct input of the second flip-flop and may be arranged to output the level “1” in response to F1?F2 and the level “0” in response to F1>F2. An output of the second overphase detection unit may be connected to a direct input of the first flip-flop and may be arranged to output the level “1” in response to F2?F1 and the level “0” in response to F2>F1.

Abstract: A diagnostic apparatus comprises a diagnostic data buffer constituting a volatile memory, and a non-volatile memory capable of receiving data from the buffer. A data buffer controller is also provided and is operably coupled to the buffer and has an event alert input and a data channel monitoring input for receiving diagnostic data. The buffer receives, when the state of a buffer status memory indicates that the buffer is in an unprotected state, at least part of the diagnostic data received by the controller via the data channel monitoring input to the buffer and the controller sets the state of the buffer status memory to indicate the protected state in response to receipt of an event alert received via the event alert input. A controller monitors the buffer status memory and copies a portion of the buffer to the non-volatile memory in response to the buffer status memory being set to be indicative of the protected state.

Abstract: A microcontroller unit (MCU) having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.

Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.