Patents Assigned to Freescale Semiconductor
  • Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
    Patent number: 9299670
    Abstract: A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 29, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weng F. Yap, Michael B. Vincent, Jason R. Wright
  • Semiconductor device having lead frame with notched inner leads
    Patent number: 9299645
    Abstract: A semiconductor device is assembled from a lead frame. The device has a semiconductor die mounted on a flag of the lead frame. A mold compound forms a housing that covers the die. Lead fingers surround the die. Each lead finger has an inner lead length that is covered by the housing and an outer lead length that protrudes from the housing. The inner lead length extends from an edge of the housing towards the die. The inner lead length has an intermediate region that has been bent to form a notch. Bond wires electrically connect electrodes of the die to respective inner lead lengths.
    Type: Grant
    Filed: November 23, 2014
    Date of Patent: March 29, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lei Wang, Liping Guo, Jinsheng Wang
  • Oscillator circuit, a semiconductor device and an apparatus
    Patent number: 9300302
    Abstract: An oscillator circuit for providing an output clock signal is described. The oscillator circuit comprising a voltage reference, a first current source, first capacitor, first capacitor switch, second current source, second capacitor, second capacitor switch, first comparator, second comparator and flip-flop. The first comparator comprises a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in a first half-phase of the output clock signal to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and in the zeroing phase in the second half-phase.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: March 29, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hubert Bode, Mathieu Lesbats
  • Built-in self test (BIST) with clock control
    Patent number: 9298572
    Abstract: A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: March 29, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nisar Ahmed, Anurag Jindal, Nipun Mahajan
  • COPPER WIRE THROUGH SILICON VIA CONNECTION
    Publication number: 20160086880
    Abstract: A semiconductor device includes a semiconductor substrate having opposing first and second main surfaces, a via (TSV) extending from the first main surface of the substrate to the second main surface of the substrate, first electrical connectors formed near the first main surface and second electrical connectors formed near the second main surface. There are insulated bond wires, each extending through the via and having a first end bonded to a respective one of the first electrical connectors and a second end bonded to a respective one of the second electrical connectors. The via may be filled with an encapsulating material.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Navas Khan Oratti Kalandar, Wai Yew Lo, Wen Shi Koh
  • CELL MONITORING APPARATUS, BATTERY MONITORING APPARATUS, INTEGRATED CIRCUIT AND METHOD OF MONITORING A RECHARGEABLE CELL
    Publication number: 20160084913
    Abstract: A cell monitoring apparatus includes a processor and memory arranged to execute code representing a linear time-invariant state transition model and a non-linear observation model are provided to model a rechargeable cell using at least a non-linear open circuit voltage, an internal resistance, a time-invariant distortion voltage across a reactive component block, and a distortion current component constituting an error of measurement of current flowing through the reactive component block. An estimator unit performs extended Kalman filtering in respect of the state transition model and the observation model using the input state data in order to generate output state data. The processor is arranged to evaluate a criterion associated with at least part of the output state data and to generate a control signal in response to evaluation of the criterion.
    Type: Application
    Filed: May 29, 2013
    Publication date: March 24, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Michael HUTTERER, Savino Luigi LUPO, Antonino LEONE
  • FAN-OUT WAFER LEVEL PACKAGE CONTAINING BACK-TO-BACK EMBEDDED MICROELECTRONIC COMPONENTS AND ASSEMBLY METHOD THEREFOR
    Publication number: 20160086930
    Abstract: Fan-Out Wafer Level Packages (FO-WLPs) include double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship. In one embodiment, the FO-WLP fabrication method includes positioning a first microelectronic component carried by a first temporary substrate in a back-to-back relationship with a second microelectronic component carried by a second temporary substrate. The first and second components are overmolded while positioned in the back-to-back relationship to produce a double-sided molded package body. The first temporary substrate is then removed to expose a first principal surface of the package body at which the first component is exposed, and the second temporary substrate is likewise removed to expose a second, opposing principal surface of the package body at which the second component is exposed.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Dominic Koey, Zhiwei Gong
  • LOW VOLTAGE SWING BUFFER
    Publication number: 20160085261
    Abstract: An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. The apparatus includes a third circuit of the second type to couple the output node to a second power supply node in response to a second value of the first signal. The apparatus includes a control circuit that generates the control signal based on the first signal and an output signal on the output node. The first, second, and third circuits generate an output signal on the output node. The output signal has a second voltage swing less than the first voltage swing.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Hector Sanchez
  • Viterbi decoding device and method for decoding a signal produced by a convolutional encoder
    Patent number: 9294134
    Abstract: A Viterbi decoding device to decode a signal produced by a convolutional encoder is described. The device may include: an analog-to-digital conversion unit to extract a soft symbol S=(S0, S1) from the signal, the soft symbol including a first sample value S0 and a second sample value S1; and a digital processing unit to compute, for each of the N states, a branch metric value of BM—0_K in dependence on the soft symbol S, K being an index identifying the respective state. The digital processing unit may store the soft symbol S as a complex number S=S0+J*S1 in a complex number format; and compute a complex branch metric value BM—0_(K, K?)=BM—0_K+J*BM—0_K? in a complex number format on the basis of the soft symbol S, with K different from K?.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mihai-Ionut Stanciu, Ioan-Virgil Dragomir, Khurram Waheed
  • Reducing MEMS stiction by deposition of nanoclusters
    Patent number: 9290380
    Abstract: A mechanism for reducing stiction in a MEMS device by decreasing surface area between two surfaces that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of one or both of the surfaces. The increased roughness is provided by forming a micro-masking layer on a sacrificial layer used in formation of the MEMS device, and then etching the surface of the sacrificial layer. The micro-masking layer can be formed using nanoclusters. When a next portion of the MEMS device is formed on the sacrificial layer, this portion will take on the roughness characteristics imparted on the sacrificial layer by the etch process. The rougher surface decreases the surface area available for contact in the MEMS device and, in turn, decreases the area through which stiction can be imparted.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Ruben B. Montez
  • Pressure sensor with differential capacitive output
    Patent number: 9290067
    Abstract: A MEMS pressure sensor device is provided that can provide both a linear output with regard to external pressure, and a differential capacitance output so as to improve the signal amplitude level. These benefits are provided through use of a rotating proof mass that generates capacitive output from electrodes configured at both ends of the rotating proof mass. Sensor output can then be generated using a difference between the capacitances generated from the ends of the rotating proof mass. An additional benefit of such a configuration is that the differential capacitance output changes in a more linear fashion with respect to external pressure changes than does a capacitive output from traditional MEMS pressure sensors.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Andrew C. McNeil, Yizhen Lin
  • VOLTAGE REGULATION SYSTEM FOR INTEGRATED CIRCUIT
    Publication number: 20160077533
    Abstract: An integrated circuit (IC) includes a power grid having first, second, third, and fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively. A feedback circuit is connected to the second and fourth nodes for receiving the second supply and second ground voltage signals and generating a feedback voltage signal based on a difference between the second supply and second ground voltage signals. A resistor-ladder network receives the feedback signal and generates a sense voltage signal. A voltage regulator compares the sense voltage signal with a reference voltage signal and regulates the first supply voltage signal at a first voltage level.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 17, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Nishant Singh Thakur
  • RECEIVER SYSTEM AND METHOD FOR RECEIVER TESTING
    Publication number: 20160077196
    Abstract: A receiver system which may be implemented in an integrated circuit device and suitable for use in automotive radar systems such as collision avoidance systems, includes self test circuitry whereby a local oscillator test signal is generated by an on-board frequency multiplier and mixed in a down-conversion mixer with an RF test signal. The RF test signal is generated on the device by up-conversion of an externally generated low-frequency test signal with the local oscillator test signal. Baseband components may also be checked using test signals of suitable frequency divided down from the local oscillator test signal by a programmable frequency divider. This self test arrangement obviates any need for applying externally generated RF test signals to the IC device.
    Type: Application
    Filed: May 29, 2013
    Publication date: March 17, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Bernhard DEHLINK, Akbar GHAZINOUR, Ralf REUTER
  • DEVICE HAVING A SECURITY MODULE
    Publication number: 20160078253
    Abstract: A device securely accesses data in a memory via an addressing unit which provides a memory interface for interfacing to a memory, a core interface for interfacing to a core processor and a first and second security interface. The device includes a security processor HSM for performing at least one security operation on the data and a remapping unit MMAP. The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. The device provides a clear view on encrypted memory data without requiring system memory for storing the clear data.
    Type: Application
    Filed: April 30, 2013
    Publication date: March 17, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Juergen FRANK, Michael STAUDENMAIER, Manfred THANNER
  • Sensor Protective Coating
    Publication number: 20160075553
    Abstract: A microelectromechanical system (MEMS) sensor device includes a substrate, a support structure supported by the substrate, a membrane supported by the support structure and spaced from the substrate, and a polymer layer covering the membrane.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 17, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Dubravka Bilic, Stephen R. Hooper
  • Test structure and methodology for estimating sensitivity of pressure sensors
    Patent number: 9285404
    Abstract: A test structure includes two capacitor structures, wherein one of the capacitor structures has conductor plates spaced apart by a cavity, and the other capacitor structure does not include a cavity. Methodology entails forming the test structure and a pressure sensor on the same substrate using the same fabrication process techniques. Methodology for estimating the sensitivity of the pressure sensor includes detecting capacitances for each of the two capacitor structures and determining a ratio of the capacitances. A critical dimension of the cavity in one of the capacitor structures is estimated using the ratio, and the sensitivity of the pressure sensor is estimated using the critical dimension.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 15, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chad S. Dawson, Peter T. Jones, Bruno J. Debeurre
  • Final result checking for system with pre-verified cores
    Patent number: 9286180
    Abstract: Provided are a system and method for generating final result checking for a test case. A test case is executed for a coherent memory system having a processor core. An event log is generated for the processor core. The event log is analyzed. The test case for the core is annotated with a checker for performing expected data checking for physical addresses modified by the processor core.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: March 15, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Aditya Musunuri, Amol V. Bhinge
  • Packaged semiconductor device
    Patent number: 9287200
    Abstract: A packaged semiconductor device includes a lead frame having a plurality of leads; a semiconductor die mounted onto the lead frame; and an encapsulant surrounding the semiconductor die. At least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead includes a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 15, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Leo M. Higgins, III
  • System and method for improved job processing to reduce contention for shared resources
    Patent number: 9286118
    Abstract: A method of processing a job is presented. A packet selector determines a candidate job list including an ordered listing of candidate jobs. Each candidate job in the ordered listing belongs to a communication stream. One or more shared resources required for execution of a first job in the candidate job list are identified. Whether the first job is eligible for execution is determined by determining an availability of the one or more shared resources required for the first job, and, when the one or more shared resource required for the first job are unavailable and no jobs executing within the data processor are from the same communication stream as the first job, determining that the first job is not eligible for execution.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: March 15, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Timothy G. Boland, Anne C. Harris, Steven D. Millman
  • METHOD, COMPUTER PROGRAM PRODUCT AND CONTROLLER FOR STARTING-UP A SWITCHED RELUCTANCE MOTOR, AND ELECTRICAL APPARATUS IMPLEMENTING SAME
    Publication number: 20160072413
    Abstract: A method of starting-up a switched reluctance, SR, motor is provided. The method comprises simultaneously energizing a plurality of phases at a first time point with respective phase voltages that are substantially the same, until the motor rotor is stabilized in alignment with either one of the plurality of phases; simultaneously de-energizing the plurality of phases at a second time point that follows the first time point; monitoring a decrease of respective phase currents in the plurality of phases from a third time point that follows the second time point by a first predetermined time interval; determining a phase of alignment of the rotor using evaluation of the decrease of the phase currents following simultaneous de-energizing of the plurality of phases; and, initiating rotation of the rotor from the determined phase of alignment of the rotor.
    Type: Application
    Filed: April 22, 2013
    Publication date: March 10, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Pavel GRASBLUM