Abstract: Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.

Abstract: A voltage regulation subsystem for a microprocessor has both internal and external regulation modes. An internal auxiliary voltage regulator is selectively enabled to overdrive the voltage. The enablement of the auxiliary voltage regulator is contingent upon a comparison of bandgap references of the internal and external regulators used in the respective regulation modes, which boosts the supply voltage, enables circuitry supplied by the external regulator (with the assistance of auxiliary voltage regulators) to boot robustly in extreme Process-Voltage-Temperature (PVT) conditions.

Abstract: A method of automatically generating a set of test layouts for testing a design rule checking tool is described. A layout is a point in a space of several coordinates, and the design rule comprises N design constraints numbered 1 to N, wherein N is greater or equal two and each design constraint is a boolean-valued function of one or more of the coordinates. The set of test layouts includes: one or more zero-error layouts; one or more one-error layouts; and one or more two-error layouts. A zero-error layout is a layout that satisfies all of the design constraints. A one-error layout is a layout that violates exactly one of the design constraints. A two-error layout is a layout that violates exactly two of the design constraints.

Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

Abstract: A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

Abstract: An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die (157) and surrounding scribe grid (156) to a test head (155) which is positioned over a wafer (160) in alignment with a die under test (163) and surrounding scribe grid (161, 165), such that one or more optical deflection mirrors (152, 154) in the test head scribe grid (156) are aligned with one or more optical deflection mirrors (162, 164) in the scribe grid (161, 165) for the die under test (163) to enable optical die probe testing on the die under test (163) by directing a first optical test signal (158) from the production test die (157), through the first and second optical deflection mirrors (e.g., 152, 162) and to the first die.

Abstract: A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current.

Abstract: An integrated circuit package includes a die having a first substrate implementing an integrated circuit comprising circuit elements. The die includes a first plurality of metal layers implementing a first portion of a metal interconnect structure for the integrated circuit. The die also includes a first plurality of pads at or overlying a top metal layer of the first plurality of metal layers. The integrated circuit package includes an interposer having a second plurality of metal layers implementing a second portion of the metal interconnect structure. The interposer includes a second plurality of pads at or overlying a top metal layer of the second plurality of metal layers. A plurality of solder structures couple the first and second pluralities of pads. The first and second portions of the metal interconnect structure together complete a signal path between two or more circuit blocks of the integrated circuit.

Abstract: A compute engine is arranged to retrieve a block of image data corresponding to a rectangular image region; calculate integral image values for all pixels of the block of image data to obtain an integral image of the block of image data; and store the integral image of the block in the one or more memories. The main processor determines which blocks of image data comprise pixels of the predefined rectangular region of the image, and defines a respective rectangular region part as the pixels of the block that belong to the predefined rectangular region of the image; calculate a HAAR feature of the rectangular region part for each block of image data that comprise pixels of the predefined rectangular region of the image; and add the HAAR features of the rectangular region parts to obtain the HAAR feature of the predefined rectangular region of the image.

Abstract: A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.

Abstract: A current generator circuit includes at least one current generation component arranged to generate an output current of the current generator circuit, at least one absolute current calibration component arranged to enable calibration of an absolute current value of the output current, and at least one temperature coefficient calibration component arranged to enable calibration of a temperature coefficient characteristic of the output current. The at least one temperature coefficient calibration component is further arranged to be in a passive state at a reference temperature.

Abstract: In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated.

Abstract: A variable-bias power amplifier is provided, comprising: a first variable voltage source generating first bias voltages based on bias control signals; a first amplifier circuit amplifying an output RF signal to generate a first amplified signal based on the first bias voltages; a second variable voltage source generating second bias voltages based on the bias control signals; a second amplifier circuit amplifying the output RF signal to generate a second amplified signal based on the second bias voltages; and a DC isolation circuit between the first amplifier circuit and the second amplifier circuit, electrically isolating DC currents at the first amplifier from DC currents at the second amplifier, wherein the first variable voltage source can be controlled independently from the second variable voltage source, and the first amplifier circuit, the second amplifier circuit, and the DC isolation circuit are all formed on a single die.

Abstract: A method and apparatus are used to predistort input signal samples according to Volterra Series Approximation Model using one or more digital predistortion blocks (300) having a plurality of predistorter cells (301-303), each including an input multiplication stage (366-367) for combining absolute sample values received from an absolute sample delay line (362) into a first stage output, a lookup table (368) connected to be addressed by the first stage output for generating an LUT output, and a plurality of output multiplication stages (371-372, 373-374) for combining the LUT output with samples received from the amplitude sample delay line (362) and signal sample delay line (363) to generate an output signal sample yQ from said predistorter cell, where the output signal samples yQ from the predistorter cells are combined at an output adder circuit (375) to generate one or more Volterra terms of a combined signal (yOUT[n]).

Abstract: A controller executes a first LBIST test on a device at a first shift frequency on a plurality of partitions and detects any voltage drop at sense points in each partition during the test. If a voltage drop is detected, then the test is re-run for those partitions that failed the first test. If failures are detected during the re-execution, then a further test at a lower shift frequency is performed. The partitions can be tested sequentially or in parallel and invention has the advantage of reducing the time taken for executing LBIST when the device is booted.

Abstract: A semiconductor sensor device includes a device substrate, a micro-controller unit (MCU) die attached to the substrate, and a packaged pressure sensor having a sensor substrate and a pressure sensor die. The sensor substrate has a front side with the pressure sensor die attached to it, a back side, and an opening from the front side to the back side. A molding compound encapsulates the MCU die, the device substrate, and the packaged pressure sensor. A back side of the sensor substrate and the opening in the sensor substrate are exposed on an outer surface of the molding compound.

Abstract: An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.

Abstract: A method for assembling a thin, flexible integrated circuit (IC) device includes using an etched contoured lead frame having raised features. A die is attached to the lead frame to form a sub-assembly that is then selectively coated with a low-modulus gel. The sub-assembly is covered with a temporary mask for sputter deposition of a metallic seed layer for interconnects between the die and the raised features. The mask is removed and more robust metal interconnects are grown over the seed paths using electroplating. The sub-assembly top is then coated with another gel layer. The bottom of the sub-assembly and of the contoured lead frame is removed, which transforms the raised features into leads. The newly exposed bottom of the sub-assembly is covered with a third layer of gel to complete assembly of the packaged device.

Abstract: A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. The shielding wire (or wires) provide active shielding to the guarded wire by simultaneously transmitting the same signal as the guarded wire between the multi-wire lead the multi-site bond pad.

Abstract: A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.