Patents Assigned to Freescale Semiconductor
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Patent number: 9236344Abstract: A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.Type: GrantFiled: December 15, 2014Date of Patent: January 12, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Douglas M. Reber, Mehul D. Shroff, Edward O. Travis
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Patent number: 9236363Abstract: A semiconductor device includes a substrate, first and second bond pad structures supported by the substrate and spaced from one another by a gap, and a wire bond foot jumper extending across the gap and bonded to the first and second bond pad structures.Type: GrantFiled: March 11, 2014Date of Patent: January 12, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Jeffrey K. Jones, Basim H. Noori, Mohd Salimin Sahludin, Fernando A. Santos
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Patent number: 9236358Abstract: An integrated circuit package comprising a substrate and at least one semiconductor die is described. A connection unit may provide electrical connections between the substrate and the semiconductor die. The connection unit may comprise a stack of conduction layers and isolation layers stacked atop each other. The stack may include a microstrip line or a coplanar waveguide. The microstrip line or the coplanar waveguide may be part of a balun, a power divider, or a directional coupler.Type: GrantFiled: August 31, 2011Date of Patent: January 12, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Ralf Reuter, Saverio Trotta
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Patent number: 9236372Abstract: An integrated circuit ESD protection circuit (270) is formed with a combination device consisting of a gated diode (271) and an output buffer MOSFET (272) where the body tie fingers of a first conductivity type (307) are formed in the substrate (301, 302) and isolated from the drain regions of a second conductivity type (310) using a plurality of diode poly fingers (231, 232) which are interleaved with a plurality of poly gate fingers (204, 205) forming the output buffer MOSFET (272).Type: GrantFiled: July 29, 2011Date of Patent: January 12, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Michael A. Stockinger
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Patent number: 9236498Abstract: A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region.Type: GrantFiled: August 27, 2014Date of Patent: January 12, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Anirban Roy, Craig T. Swift
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Patent number: 9236331Abstract: An electronic apparatus includes a packaging enclosure, first and second die pads disposed within the packaging enclosure, first and second semiconductor die disposed on the first and second die pads, respectively, a plurality of packaging leads, each packaging lead projecting outward from the packaging enclosure, a plurality of packaging posts disposed within the packaging enclosure and extending inward from opposite sides of the packaging enclosure between the first and second die pads, each packaging post being connected with a respective one of the plurality of packaging leads, and a plurality of wire bonds disposed within the packaging enclosure. Each packaging post of the plurality of packaging posts is connected via a first wire bond of the plurality of wire bonds to the first semiconductor die and via a second wire bond of the plurality of wire bonds to the second semiconductor die.Type: GrantFiled: February 25, 2014Date of Patent: January 12, 2016Assignee: Freescale Semiconductor, Inc.Inventors: William E. Edwards, Gary C. Johnson
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Patent number: 9236472Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.Type: GrantFiled: April 17, 2012Date of Patent: January 12, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Weize Chen, Hubert M. Bode, Richard J. De Souza, Patrice M. Parris
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Publication number: 20160004292Abstract: A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Garima Sharda, Carl Culshaw, Alan Devine, Akshay K. Pathak, Alistair P. Robertson
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Publication number: 20160004536Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Applicant: Freescale Semiconductor Inc.Inventors: Peter J. Wilson, Brian C. Kahne, Jeffrey W. Scott
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Publication number: 20160004654Abstract: A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core.Type: ApplicationFiled: July 6, 2014Publication date: January 7, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Yashpal Dutta, Himanshu Goel, Varun Sethi
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Publication number: 20160005730Abstract: An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.Type: ApplicationFiled: September 15, 2015Publication date: January 7, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Rouying Zhan, Chai Ean Gill, Changsoo Hong, Michael H. Kaneshiro
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Publication number: 20160004661Abstract: A Universal Serial Bus (USB) controller includes a USB transceiver to detect a high-speed (HS) disconnect between the USB controller and a device connected to it. The USB transceiver includes a reference-voltage generation circuit, a HS current driver, first and second comparators, and a multiplexer. The reference-voltage generation circuit generates HS disconnect and transmitter reference-voltage signals that have a constant voltage difference. The first comparator receives DP and DM signals that correspond to a HS Start of Frame (SOF) packet during HS disconnect detection, and generates a control voltage. The multiplexer outputs at least one of the DP and DM signals based on the logic state of the control voltage. The second comparator receives the selected signal and the HS disconnect reference-voltage signal, and outputs a HS disconnect output voltage signal when the selected signal is greater than the HS disconnect reference-voltage signal.Type: ApplicationFiled: July 6, 2014Publication date: January 7, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Ravi Dixit, Parul K. Sharma
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Publication number: 20160006399Abstract: A two-way Doherty amplifier for amplifying a modulated or non-modulated carrier signal, said carrier signal having a carrier frequency; wherein the Doherty amplifier comprises a first amplifier having a first amplifier output node, a second amplifier having a second amplifier output node, a combining node connected or connectable to a load, a first amplifier output line connecting the first amplifier output node to the combining node, and a second amplifier output line connecting the second amplifier output node to the combining node, and wherein the first amplifier output line has an electrical length of substantially one quarter wavelength of the carrier signal and the second amplifier output line has an electrical length of substantially one half wavelength of the carrier signal.Type: ApplicationFiled: January 10, 2013Publication date: January 7, 2016Applicant: Freescale Semiconductor, Inc.Inventor: IGOR BLEDNOV
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Patent number: 9232156Abstract: A video processing device for generating an output video stream on the basis of two or more concurrent input video streams and a method thereof are described. Each input video stream comprises a sequence of input images. The output video stream comprises a sequence of output images. The video processing device generates each output image by merging a respective set of input images. The set of input images comprises one input image from each input video stream. The video processing device merges the input images in a series of merging rounds. Each merging round comprises forming an output tile by merging a set of input tiles, and writing the output tile to an output memory unit. The set of input tiles comprises one input tile from each input image of the respective set of input images. The output tiles written to the output memory unit represent the output image.Type: GrantFiled: September 22, 2014Date of Patent: January 5, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Michael Andreas Staudenmaier, Stephan Herrmann, Robert Cristian Krutsch
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Patent number: 9231120Abstract: A Schottky diode includes a device structure having a central portion and a plurality of fingers. Distal portions of the fingers overlie leakage current control (LCC) regions. An LCC region is relatively narrow and deep, terminating in proximity to a buried layer of like polarity. Under reverse bias, depletion regions forming in an active region lying between the buried layer and the LCC regions occupy the entire extent of the active region and thereby provide a carrier depleted wall. An analogous depletion region occurs in the active region residing between any pair of adjacent fingers. If the fingers include latitudinal oriented fingers and longitudinal oriented fingers, depletion region blockades in three different orthogonal orientations may occur. The formation of the LCC regions may include the use of a high dose, low energy phosphorous implant using an LCC implant mask and the isolation structures as an additional hard mask.Type: GrantFiled: June 29, 2012Date of Patent: January 5, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Weize Chen, Xin Lin, Patrice M. Parris
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Adaptive scheduling queue control for memory controllers based upon page hit distance determinations
Patent number: 9229885Abstract: Methods and systems are disclosed for adaptive scheduling queue control based upon page hit distance determinations. A threshold occupancy value is determined for a window of previous access requests to a memory and used to adaptively control a number of access requests stored in a scheduling queue buffer. For certain embodiments, a page hit distance (PHD) determination for each access request and historical page hit distance data is used to adjust the threshold occupancy value that determines the number (N) of access requests stored in the buffer prior to removing an access request and using it to access the memory. For each access request, the page hit distance represents the number of previously received access requests since the last access request to access the same page of memory. An average PHD can be determined over a number (M) of previous access requests and used to control the threshold occupancy value.Type: GrantFiled: May 21, 2014Date of Patent: January 5, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Arup Chakraborty, Jaksa Djordjevic -
Patent number: 9229884Abstract: A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g., 14, 61) by executing a control instruction (47, 48) to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned device (14, 61) can determine if the access command can be performed based on local access control information.Type: GrantFiled: April 30, 2012Date of Patent: January 5, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
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Patent number: 9231083Abstract: A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).Type: GrantFiled: June 29, 2012Date of Patent: January 5, 2016Assignee: FREESCAL SEMICONDUCTOR INC.Inventors: Hongning Yang, Daniel J. Blomberg, Jiang-Kai Zuo
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Patent number: 9231569Abstract: An apparatus is provided. The apparatus includes a flip-flop including an input configured to receive a setup time and delay control (SDC) signal, and an output buffer including first and second conductive paths. The second conductive path is non-conductive when the SDC signal has a first value at the input and is conductive when the SDC signal has a second value at the input. The apparatus includes a propagation delay sensor configured to estimate a propagation delay of the flip-flop, and, when the estimated propagation delay exceeds a threshold, supply the SDC signal having the second value to the input of the flip-flop.Type: GrantFiled: January 24, 2013Date of Patent: January 5, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Alexandro Giron Allende
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Publication number: 20150378385Abstract: An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Manmohan Rana, Rakesh Pandey, Nishant Singh Thakur