Abstract: A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively.

Abstract: A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory [NVM] comprising a plurality of NVM lines.

Abstract: The embodiments described herein provide a radio frequency (RF) driver amplifier and method of operation. In general, the driver amplifier facilitates high performance operation in RF devices while being implemented with only n-type transistors. Using only n-type transistors in the driver amplifier can increase the operating bandwidth of the driver amplifier. Furthermore, using only n-type transistors in the driver amplifier can simplify device fabrication. The driver amplifiers and methods described herein can be used in a variety of applications. As one specific example the driver amplifier can be used in a switch-mode power amplifier (SMPA). Such a SMPA can be configured to amplify a time varying signal, such as an RF.

Abstract: A ground-loss detection circuit for an integrated circuit, (IC) device including a first dynamic threshold metal oxide semiconductor (DTMOS) device operably coupled between a first ground plane of the IC device and at least one further ground plane of the IC device, at least one of the first and at least one further ground planes comprising an external ground connection of the IC device, at least one further DTMOS device operably coupled between the first and at least one further ground planes of the IC device in an opposing manner to the first DTMOS device, and at least one ground-loss detection component operably coupled to at least one of the first and at least one further DTMOS devices and arranged to detect a ground-loss for at least one of the first and at least one further ground planes based at least partly on a drain current of the at least one of the first and at least one further DTMOS device(s).

Abstract: A integrated circuit device has at least one instruction processing module arranged for executing vector data processing upon receipt of a respective one of a set of data processing instructions. The data processing instructions include at least one matrix processing instruction for processing elements of a matrix. The elements of rows of the matrix are stored in a set of register, and the instruction processing module comprising an accessing unit for accessing selected elements of the matrix, which selected elements are non-sequentially located according to a predetermined pattern across multiple registers of the set of registers, the accessing enabling respective processing lanes to write or read different registers. Advantageously elements in columns of a matrix can efficiently be processed.

Abstract: A device includes a Doherty amplifier having a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a variable impedance coupled to an output of the Doherty amplifier, and a controller configured to set the variable impedance to a first impedance when an output power level of the Doherty amplifier is less than a threshold and to a second impedance when the output power level of the Doherty amplifier is above the threshold.

Abstract: A communication device (1) for a wideband code division multiple access communication (W-CDMA) system is described. The communication device has an antenna interface (AIF), a front end processor (FE), a packet generator (PG), a packet writer (PW) and one or more digital signal processors (DSP1, DSP2). The front end processor (FE) is configured to receive one or more antenna signals from the antenna interface (AIF) and to calculate soft symbols representing symbols transmitted by a UE (UE0, UE1) using descrambling and despreading of the one or more antenna signals using a plurality of fingers assigned to the UE. The packet generator (PG) is configured to organize the soft symbols into packets, each packet comprising the soft symbols from the plurality of fingers assigned to a respective UE associated with one physical channel of the one of more physical channels and with the same symbol index. The packet writer (PW) is configured to write the packets into a system memory (SYSMEM).

Abstract: To facilitate dynamic lockstep support, replacement states and/or logic used to select particular cache lines for replacement with new allocations in accord with replacement algorithms or strategies may be enhanced to provide generally independent replacement contexts for use in respective lockstep and performance modes. In some cases, replacement logic that may be otherwise conventional in its selection of cache lines for new allocations in accord with a first-in, first-out (FIFO), round-robin, random, least recently used (LRU), pseudo LRU, or other replacement algorithm/strategy is at least partially replicated to provide lockstep and performance instances that respectively cover lockstep and performance partitions of a cache. In some cases, a unified instance of replacement logic may be reinitialized with appropriate states at (or coincident with) transitions between performance and lockstep modes of operation.

Abstract: Systems and methods for indicating internal transmitter errors in a Controller Area Network (CAN). In some embodiments, a method may include initiating, by a device coupled to a CAN, transmission of a message via the CAN; detecting an error by the device during the transmission; and continuing, by the device after having detected the error, the transmission of the message without causing or indicating a bus error condition. In other embodiments, a CAN node may include message processing circuitry configured to receive a frame from a transmitter, the frame comprising a cyclic redundancy check (CRC) field, the message processing circuitry further configured to identify an internal error of the transmitter based upon the CRC field.

Abstract: A method and apparatus for calculating delay timing values for at least a part of an integrated circuit design. The method comprises applying a first Negative/Positive Bias Temperature Instability compensation margin to delay values for elements within the at least part of the IC design, identifying at least one lower-rate switching element within the at least part of the IC design, and applying at least one further, increased N/PBTI compensation margin to the delay value(s) for the at least one identified lower-rate switching element.

Abstract: An electronic device includes a set of two or more scan chains and a buffer chain. Each of the scan chains includes a sequence of stateful elements connected in series, and each of the scan chains is arranged to hold a string having a length identical to the length of the (50) respective scan chain. The strings of the scan chains are shifted in parallel from the scan chains into the memory unit and back from the memory unit into the respective scan chains. The store operation and the restore operation each include at least N0 elementary downstream shift operations. The set (100) of scan chains includes a short chain and a detour chain, wherein the short chain (C1) has a length N1 shorter than N0, and the buffer chain. The output end of the short chain is coupled to an input end of the (150) buffer chain. The buffer chain is provided at least partly by the detour chain.

Abstract: An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

Abstract: A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

Abstract: There is provided a multimedia computing apparatus for processing and displaying video data with overlay graphic data, said multimedia computing apparatus comprising a compression unit arranged to compress graphic overlay data prior to storage of said compressed overlay graphic data in a compressed display buffer, and a control unit arranged to determine when to compress the overlay graphic data dependent upon a refresh parameter of the overlay graphic data. There is also provided a method of adaptively compressing graphics data in a multimedia computing system comprising dynamically controlling compression of graphic overlay data in a display buffer dependent upon a refresh parameter of the graphic overlay data.

Abstract: The present disclosure presents a device and method for connecting an RF generator to a coaxial conductor. The device includes a substrate, a radio frequency generator on the substrate, and a coaxial conductor coupled to a first surface of the substrate. The coaxial conductor includes a conductive core and a conductive shield around the conductive core and is configured to transmit the radio frequency signal to a radiation device. The device includes a cap coupled to the substrate and extending from a second surface of the substrate opposite the first surface. The cap includes an outer wall and a center post. The outer wall is electrically connected to the conductive shield of the coaxial conductor and the center post is electrically connected to the conductive core of the coaxial conductor. An output pad of the radio frequency generator is electrically connected to the conductive core.

Abstract: In general the embodiments described herein can provide alternating-current (AC) resonating filters. These resonating filters comprise a transmission line, a first resonator, and a second resonator. The first resonator is configured to block AC signals in a first frequency range, while the second resonator is configured to block AC signals in a second frequency range, where the second frequency range is higher than the first frequency range. The transmission line has a first node coupled to an AC source, and the first resonator is coupled to the transmission line a first distance from the first node, and the second resonator is coupled to the transmission line a second distance from the first node, where the second distance is greater than the first distance. When so configured the resonating filter can effectively block signals in multiple selected frequency bandwidths.

Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a transmission configuration. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in various transmission configurations.

Abstract: A device simulation system performs a set of tests by applying, for each test in the set, a corresponding test stimulus to a simulation of the electronic device. In response to each test stimulus, the simulation generates corresponding output information which the device simulation system compares to a specified expected outcome to identify a test result for that test stimulus. In addition, for each test stimulus, the device simulation system generates test coverage information indicating the particular configuration of the simulated electronic device that resulted from the stimulus. The device simulation system correlates the coverage information with the test results to identify correlation rules that indicate potential relationships between test results and configurations of the simulated device.

Abstract: A method of measuring skew between signals from an asynchronous integrated flash memory controller (IFC) includes connecting input/output (I/O) pins of the IFC to cycle based test equipment (ATE). The ATE applies a pattern of test signals as input drive to the IFC. Relative to the test cycle, the earliest delay time at which output signals from all of the I/O pins first correspond with expected results, and the latest delay time at which the output signals still correspond with the expected results are measured. The difference between the latest and the earliest delay times is compared with a limit value and a comparison report is generated.

Abstract: An adjustable power splitter includes: a power divider with an input and a plurality, N, of divider outputs; a plurality, N, of adjustable phase shifters and a plurality, N, of adjustable attenuators series coupled to the divider outputs and providing a plurality, N, of power outputs; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the adjustable phase shifters and attenuation levels to be applied by the adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the adjustable phase shifters and the adjustable attenuators.