Patents Assigned to Freescale Semiconductor
  • STORAGE AND RETRIEVAL OF INFORMATION USING INTERNET PROTOCOL ADDRESSES
    Publication number: 20150295883
    Abstract: A method for storing information in a memory using an IP address having numerical fields, where penultimate and ultimate memory banks for the IP address are allocated from the memory. A penultimate pointer is stored in a location of the penultimate memory bank indexed by the value of a penultimate numerical field in the IP address. The penultimate pointer points to the ultimate memory bank. The information is stored in a location of the ultimate memory bank indexed by the value of an ultimate numerical field in the IP address.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 15, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Chandra Sekhar Suram, Rampullaiah Batchu, Nitin K. Parikh, Jyothi Vemulapalli
  • DATA PROCESSING DEVICE, METHOD OF EXECUTION ERROR DETECTION AND INTEGRATED CIRCUIT
    Publication number: 20150293807
    Abstract: A data processing device provided with an error detection unit includes a processor arranged to support execution of an operation including a first sequence of instructions and execution of a second sequence of instructions implementing the operation, the first and second sequences of instructions generating, when in use, a first result and a second result, respectively. Configurable circuitry is also provided and arranged to support a repository to receive the first result and the second result following generation thereof. The configurable circuitry is configured as a function comparator unit arranged to compare the first and second results for consistency and to control further execution of the first implementation and the second implementation in response to a result of the comparison.
    Type: Application
    Filed: November 22, 2012
    Publication date: October 15, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: John RALSTON
  • Matrix lid heatspreader for flip chip package
    Patent number: 9159643
    Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: George R. Leal, Tim V. Pham
  • Chip damage detection device for a semiconductor integrated circuit
    Patent number: 9157955
    Abstract: A chip damage detection device is provided that includes at least one bi-stable circuit having a first conductive line passing through an observed area of a semiconductor integrated circuit chip for damage monitoring of the observed area. The at least one bi-stable circuit is arranged to flip from a first stable state into a second stable state when a potential difference between a first end and a second end of the first conductive line changes or when a leakage current overdrives a state keeping current at the first conductive line. Further, a semiconductor integrated circuit device that includes the chip damage detection device and a safety critical system that includes the semiconductor integrated circuit device or the chip damage detection circuit is provided.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: October 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Erwan Hemon, Philippe Lance, Kurt Neugebauer
  • Flexible control mechanism for store gathering in a write buffer
    Patent number: 9158725
    Abstract: A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: October 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Quyen Pho
  • Semiconductor device with HCI protection region
    Patent number: 9159803
    Abstract: A device includes a semiconductor substrate, a drift region in the semiconductor substrate and having a first conductivity type, an isolation region within the drift region, and around which charge carriers drift on a path through the drift region during operation, and a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Hongning Yang, Jiangkai Zuo
  • Die-to-die inductive communication devices and methods
    Patent number: 9160423
    Abstract: Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: October 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Fred T. Brauchler, Randall C. Gray
  • Packaged leadless semiconductor device
    Patent number: 9159588
    Abstract: A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. The frame structure is combined with the flange so that a lower surface of the flange and a lower section of each terminal pad are in coplanar alignment, and so that an upper section of each terminal pad overlies the flange. Interconnects interconnect the die with the upper section of the terminal pad. An encapsulant encases the frame structure, flange, die, and interconnects with the lower section of each terminal pad and the lower surface of the flange remaining exposed from the encapsulant.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Audel A. Sanchez, Fernando A. Santos, Lakshminarayan Viswanathan
  • DEFECTIVE DIE REPLACEMENT IN A DIE STACK
    Publication number: 20150287653
    Abstract: The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Michael B. McShane, Tim V. Pham
  • Test Mode Entry Interlock
    Publication number: 20150285858
    Abstract: An integrated circuit haying normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal (204) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.
    Type: Application
    Filed: April 2, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, John M. Hall
  • TAMPER DETECTOR POWER SUPPLY WITH WAKE-UP
    Publication number: 20150286846
    Abstract: A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.
    Type: Application
    Filed: April 6, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Siddi Jai Prakash, Kumar Abhishek, Prashant Bhargava, Michael A. Stockinger
  • METHOD AND APPARATUS FOR DRIVING A POWER TRANSISTOR GATE
    Publication number: 20150288356
    Abstract: A gate drive circuit includes a first switch electrically coupled to a single-supply input voltage node, the first switch electrically coupling the voltage node with a first capacitor if switched on; a second switch electrically coupled to a ground node, the second switch electrically coupling the first capacitor with the ground node if switched on; and the first capacitor. A first capacitor lead of the first capacitor is electrically coupled to the first and second switches and a second capacitor lead of the first capacitor is arranged to connect with a power transistor gate.
    Type: Application
    Filed: October 31, 2012
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Thierry Sicard, Philippe Perruchoud
  • SEMICONDUCTOR WAFER AND METHOD OF CONCURRENTLY TESTING CIRCUITS FORMED THEREON
    Publication number: 20150287656
    Abstract: A semiconductor wafer has an array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring. Each die has a group of bond pads and test pads coupled to the bond pads. A test pad region is formed on the wafer. The test pad region has probe pads and common electrical interconnects that selectively electrically couple each of the probe pads to a bond pad on each of the dies. The common electrical interconnects in the test pad region reduce the possibility of probe damage to the integrated circuits and allow the dies to be tested concurrently before being cut from the wafer.
    Type: Application
    Filed: May 28, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Dewey Killingsworth
  • Solder Pad for Semiconductor Device Package
    Publication number: 20150287685
    Abstract: A solder ball pad for mounting a solder ball of a semiconductor device for preventing delamination of an overlying dielectric layer, and particularly devices and methods providing improved solder ball pad structures in a device such as a semiconductor device package.
    Type: Application
    Filed: April 2, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Vijay Sarihan, Zhiwei Gong, Scott M. Hayes
  • Collapsible Probe Tower Device and Method of Forming Thereof
    Publication number: 20150287654
    Abstract: A collapsible probe tower device and methods of forming thereof, are disclosed. In one example embodiment, a method of forming a device includes providing a semiconductor die substrate having a contact pad and a probe pad, wherein the contact pad and probe pad are adhered to the substrate, forming a contact bump by applying a conductive material to a contact structure surface of a contact tower, wherein the contact tower includes the contact pad, forming a probe bump by applying a conductive material to a probe structure surface of a probe tower, wherein the probe tower includes the probe pad, and heating the conductive material that forms the contact bump and the probe bump to provide a first reflow, wherein after the first reflow, the height of a top surface of the probe bump exceeds the height of a top surface of the contact bump.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Trent S. Uehling, Kelly F. Folts
  • SEMICONDUCTOR WAFER AND METHOD OF CONCURRENTLY TESTING CIRCUITS FORMED THEREON
    Publication number: 20150287655
    Abstract: A semiconductor wafer has a non-uniform array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring, and each die has a group of bond pads and probe pad coupled to the bond pads. Common electrical interconnects selectively electrically couple together respective probe pads of each of the dies. The common electrical interconnects allow the dies to be tested concurrently before being cut from the wafer.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Dewey Killingsworth
  • INTEGRATED CIRCUIT WITH LBIST SUB-PARTITIONS
    Publication number: 20150285859
    Abstract: A Logic Built-In Self-Test (LBIST) domain of an integrated circuit is divided into partitions that in turn are subdivided into sub-partitions. Each sub-partition has an associated clock gating logic circuit that enables or inhibits the clock signal supplied to scan chains within the sub-partition. A user-defined number of sub-partitions, which can be specified on the basis of silicon results and power requirements of the integrated circuit, may be activated at any one time during a portion of an LBIST execution, which reduces toggling of concurrent scan chains, resulting in a reduction of energy consumption during testing, and reduces voltage droop due to inertia of power management control modules at the start of an LBIST test.
    Type: Application
    Filed: April 6, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Reecha Jajodia, Gagan Anand, Anurag Jindal
  • CLOCK DISTRIBUTION ARCHITECTURE FOR INTEGRATED CIRCUIT
    Publication number: 20150288366
    Abstract: An integrated circuit (IC) includes multiple circuit modules that have specific clocking requirements, multiple clock sources (e.g., PLLs, duty cycle re-shaper, etc.), and at least one clock input port. The clock sources have specific clock source specifications, and the circuit modules have specific clocking requirements. The clock sources are selected based on an identification of the most common clocking requirements, and then placed at routing distances measured from the input port that are less than corresponding predetermined maximum routing distances such that the clocking requirements of the circuit modules are met. The IC thus generates clock signals internally, rather than externally.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Amit Aggarwal, Himanshu Goel, Ashish Malhotra, Ankit Pal
  • CAVITY-DOWN PRESSURE SENSOR DEVICE
    Publication number: 20150285702
    Abstract: A cavity-down pressure sensor device has a pressure-sensing die that is electrically connected to a master control unit (MCU) using face-to-face bonding. Connecting the pressure-sensing die in this manner avoids the need to wire bond the pressure-sensing die to the master control unit.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Wai Yew Lo
  • MEMORY ACCESS SCHEME FOR SYSTEM ON CHIP
    Publication number: 20150286525
    Abstract: Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.
    Type: Application
    Filed: April 6, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Nitin Singh, Gaurav Jain, Amit Jindal, Rohit Tomar