Patents Assigned to Freescale
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Patent number: 7276406Abstract: A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film. A second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench. The presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a <100> or <110> semiconductor-on-insulator substrate.Type: GrantFiled: October 29, 2004Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Jian Chen, Michael D. Turner, James E. Vasek
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Patent number: 7277449Abstract: An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address.Type: GrantFiled: July 29, 2002Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Ned D. Garinger, Martin L. Dorr, Mark W. Naumann, Gary A. Walker
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Patent number: 7277972Abstract: One embodiment of the present invention provides a flexible peripheral access protection mechanism within a data processing system (10) in order to obtain a more secure operating environment. For example, the data processing system may include a combination of secure (12) and unsecure bus masters (14, 15) needing to access shared peripherals (22, 24). One embodiment allows for the dynamic update by a secure bus master (12) of access permissions corresponding to each unsecure bus master for each peripheral. A secure bus master is therefore able to establish which unsecure bus masters have permission to access which peripheral in order to protect the data processing system from corruption due to errant or hostile software running on unsecure bus masters. Through the use of a bus master identifier (36), access to the requested peripheral is either allowed or denied based on the permissions established by the secure bus master.Type: GrantFiled: March 8, 2002Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons
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Article comprising an oxide layer on a GaAs-based semiconductor structure and method of forming same
Patent number: 7276456Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide.Type: GrantFiled: May 25, 2005Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Matthias Passlack, Nicholas William Medendorp, Jr. -
Patent number: 7276420Abstract: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.Type: GrantFiled: July 11, 2005Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Lianjun Liu, Qiang Li, Melvy F. Miller, Sergio P. Pacheco
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Patent number: 7278062Abstract: In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.Type: GrantFiled: January 9, 2003Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons, Brian M. Millar, John J. Vaglica
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Patent number: 7276974Abstract: Method and apparatus are provided for protecting radio frequency (RF) power amplifiers. A circuit (10) is provided for limiting a supply current to a first stage (Q3) of the RF power amplifier having a second stage (Q2) coupled to the first stage. The circuit comprises a comparator (14) having first and second inputs and an output, and a switching circuit (12, 20, 22, 24) having an input coupled to the output of the comparator (14) and having an output configured to couple to the first stage (Q3). The first input of the comparator (14) is configured to receive the supply current, and the second input is configured to receive a current supplied to the second stage (Q2). The comparator (14) is configured to compare a ratio of the supply current to the first stage to the current supplied to the second stage (Q2) with a predetermined value. The switching circuit (12, 20, 22, 24) is configured to limit the supply current to the first stage (Q3) when the ratio exceeds the predetermined value.Type: GrantFiled: September 8, 2005Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: David A. Newman, Benjamin R. Gilsdorf, David S. Peckham
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Patent number: 7276435Abstract: An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.Type: GrantFiled: June 2, 2006Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Scott K. Pozder, Kevin J. Hess, Ruiqi Tian, Edward O. Travis, Trent S. Uehling, Brett P. Wilkerson, Katie C. Yu
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Publication number: 20070222425Abstract: A series regulator circuit that enables detection of a voltage drop and reduces consumed current in a static state. A constant current source, which is connected to a power supply voltage line, is connected to a bipolar transistor. The bipolar transistor includes an emitter terminal and base terminal connected to a ground line via first and second resistors, respectively. The constant current source is connected to the source terminal of a PMOS transistor and the gate terminal of an NMOS transistor. The source terminal of the NMOS transistor is connected via third and fourth resistors to the base terminal of the bipolar transistor.Type: ApplicationFiled: March 21, 2007Publication date: September 27, 2007Applicant: Freescale Semiconductor, Inc.Inventor: Hiroyuki KIMURA
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Publication number: 20070223636Abstract: A device and method for phase detection are disclosed. The device includes a phase differential module that provides a phase difference signal based on the phase difference between a data signal and a reference signal. The phase difference signal is provided to a first gate of a multi-gate fin-type field effect transistor (multi-gate FinFET) of the device. A second gate of the multi-gate FinFET transistor receives a bias signal that provides a phase detection threshold. A phase adjustment signal is provided at one or both of the FinFET current electrodes based on the phase difference signal and the bias signal.Type: ApplicationFiled: March 23, 2006Publication date: September 27, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Mohamed Moosa, Leo Mathew, Sriram Kalpat
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Publication number: 20070222480Abstract: A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.Type: ApplicationFiled: March 24, 2006Publication date: September 27, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Maciej Bajkowski, George Hoekstra, Prashant Kenkare, Ravindraraj Ramaraju
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Publication number: 20070226561Abstract: A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan chain, a first latching component that is powered in a first voltage domain and a second latching component that is powered in a second voltage domain, where one of the voltage domains can be effectively shut down when the circuit device is placed in a low-voltage mode. The system test controller can control a scan controller used to scan test data in and out of the scan chain. The system test controller further can control a power controller used to manage a power down sequence and a power up sequence so as to ensure that the data retention latches are not placed in spurious states.Type: ApplicationFiled: March 23, 2006Publication date: September 27, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Milind Padhye, Darrell Carder, Bhoodev Kumar, Bart Martinec
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Publication number: 20070223376Abstract: An arbiter for a device arranged to be coupled to a serial bus, the arbiter comprising a means for obtaining identifier information associated with one more other devices coupled to the serial bus and; means for determining a priority level based upon an identifier associated with the device and identifier associated with one of the other devices.Type: ApplicationFiled: April 28, 2004Publication date: September 27, 2007Applicant: Freescale Semiconductor, Inc.Inventor: Vassily Soloviev
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Publication number: 20070224917Abstract: A polishing pad can include a first layer and a second layer. The first layer can have a first polishing surface and a first opening. The second layer can have an attaching surface and a second opening substantially contiguous with the first opening. The polishing pad can further include, a pad window lying within the first opening. The pad window can include a second polishing surface. When the pad would be attached to a platen, the first and second polishing surfaces can lie along a same plane, and an opposing surface of the pad window can abut an exterior surface of a platen window. In another aspect, a polishing apparatus can include an exterior surface of a platen window abutting the polishing pad. In still another aspect, a process of polishing can include polishing a workpiece such that the pad window contacts the workpiece and the platen window simultaneously.Type: ApplicationFiled: March 27, 2006Publication date: September 27, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Brian Bottema, Stephen Abraham, Alex Pamatat
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Publication number: 20070222498Abstract: A charge pump system including a clock circuit and a charge pump circuit is provided. The clock circuit provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node. The charge pump circuit receives the first clock and charges the charge node at a rate based on the frequency of the first clock and the load capacitance of the charge node. The memory block select signal indicates which of the memory blocks are coupled to the charge node and thus indicates the load capacitance of the charge node. The frequency of the first clock is adjusted based on the load capacitance of the selected block so that the slew rate of the charge node is about the same. Thus, the slew rate of the voltage ramp on the charge node is about the same regardless of the load capacitance.Type: ApplicationFiled: March 24, 2006Publication date: September 27, 2007Applicant: Freescale Semiconductor Inc.Inventors: Jon Choy, Tahmina Akhter
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Patent number: 7273762Abstract: A microelectromechanical (MEM) device includes a substrate, a suspension spring, a structure, and a release bridge. The suspension spring is coupled to, and suspended above, the substrate. The structure is coupled to the suspension spring and is resiliently suspended thereby above the substrate. The release bridge is coupled to the suspension spring. During sensor manufacture, the suspension spring and structure are suspended above the substrate by undergoing a release process. The release bridge is sized such that, during the release process, the structure and the suspension spring are released substantially simultaneously.Type: GrantFiled: November 9, 2004Date of Patent: September 25, 2007Assignee: Freescale Semiconductor, Inc.Inventor: Bishnu Prasanna Gogoi
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Patent number: 7274203Abstract: A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.Type: GrantFiled: October 25, 2005Date of Patent: September 25, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Kenneth P. Tumin, George E. Baker, Dale J. McQuirk, Matthew G. Stout
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Patent number: 7275148Abstract: Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.Type: GrantFiled: September 8, 2003Date of Patent: September 25, 2007Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, James M. Norris, Philip E. May, Kent Donald Moat, Raymond B. Essick, IV, Brian Geoffrey Lucas
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Patent number: 7274247Abstract: A well-bias system dynamically adjusts well-bias set points to optimal levels across an integrated circuit (IC) for enhanced power savings and component reliability during a standby or low-power mode of operation. A controller within the IC determines if the chip power supply voltage will be reduced during an imminent standby or low power mode and sets a register controlling a negative well-bias set point for asserting well-bias to charge wells of the IC accordingly. To minimize leakage current without compromising reliability, the well-bias set point is set to (1) an optimal well-bias set point if a reduced supply voltage is to be applied to the IC, or (2) a minimum well-bias set point when a nominal or high supply voltage is to be applied to the IC.Type: GrantFiled: April 4, 2005Date of Patent: September 25, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Gregory H. Ward, Mohamed S. Moosa, Mahbub M. Rashed
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Publication number: 20070215908Abstract: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.Type: ApplicationFiled: March 15, 2006Publication date: September 20, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Da Zhang, Bich-Yen Nguyen